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rev. 1.45 1/09 copyright ? 2009 by silicon laboratories si3210 si3210/si3211 p ro slic ? p rogrammable cmos slic/c odec with r inging /b attery v oltage g eneration features applications description the proslic ? is a low-voltage cmos device that provides a complete analog telephone interface ideal for customer premise equipment (cpe) applications. the proslic integrates a subscriber line interface circuit (slic), codec, and battery generation functionality into a single cmos integrated circuit. the integrated battery supply continuously adapts its output voltage to minimize power and enables the entire solution to be powered from a single 3.3 v (si3210m/si3211m only) or 5 v supply. the proslic controls the phone line through silicon labs? si3201 linefeed interface chip. si3210 features include software-configurable 5 ren internal ringing up to 90 v pk , dtmf generation and decoding, and a comprehensive set of telephony signaling capabilities for operation with only one hardware solution. the proslic is packaged in a 38-pin qfn and tssop, and the si3201 is packaged in a thermally-enhanced 16-pin soic. functional block diagram ? performs all borscht functions ? software-programmable internal balanced ringing up to 90 v pk (5 ren up to 4 kft, 3 ren up to 8 kft) ? integrated battery supply with dynamic voltage output (si3210) ?? on-chip dc-dc converter continuously minimizes power in all operating modes ?? entire solution can be powered from a single 3.3 or 5 v supply ?? 3.3 to 35 v dc input range ?? dynamic 0 to ?94.5 v output ?? low-cost inductor and high-efficiency transformer versions supported ? software-programmable linefeed parameters ?? ringing frequency, amplitude, cadence, and waveform ?? 2-wire ac impedance and hybrid ?? constant current feed (20 to 41 ma) ?? loop closure and ring trip thresholds and filtering ? software-programmable signal generation and audio processing ?? dtmf generation and decoding ?? 12 khz/16 khz pulse metering generation ?? phase-continuous fsk (caller id) generation ?? dual audio tone generators ?? smooth and abrupt polarity reversal ?? -law/a-law and 16-bit linear pcm audio ? extensive test and diagnostic features ?? multiple voice loopback test modes ?? real-time dc linefeed measurement ?? gr-909 line test capabilities ? spi and pcm bus digital interfaces ? extensive programmable interrupts ? 100% software-configurable global solution ? ideal for customer premise equipment applications ? rohs-compliant packages available ? voice-over-broadband systems: dsl, codec, wireless ? pbx/ip-pbx/key telephone systems ? terminal adapters: isdn, ethernet, usb linefeed interface control interface pcm interface pll dtmf decode gain/ attenuation/ filter tone generators compression expansion gain/ attenuation/ filter line feed control line status dc-dc converter controller (si3210 only) prog. hybrid d/a z s a/d tip ring cs sclk sdo sdi dtx drx fsync pclk reset int si3210/11 discrete components u.s. patent #6,567,521 u.s. patent #6,812,744 other patents pending ordering information see page 129. tssop pin assignments si3210/11 27 28 29 30 31 34 33 32 cs int pclk dtx fsync reset sdch/dio1 sclk sdi sdithru sdo dcff/dout dcdrv/dcsw gndd test drx 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 14 sdcl/dio2 v dda1 iref capp itipn vddd v dda2 itipp 35 36 37 38 qgnd capm iringp iringn stipdc sringdc stipe svbat sringe igmp gnda igmn sringac stipac 15 16 17 18 19 24 23 22 21 20
si3210/si3211 2 rev. 1.45
si3210/si3211 rev. 1.45 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.1. linefeed interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2. battery voltage generation and swit ching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3. tone generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4. ringing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5. pulse metering generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6. dtmf detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 2.7. audio path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 2.8. two-wire impedance matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.9. clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.10. interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.11. serial peripheral interfac e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.12. pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.13. companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4. indirect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 4.1. dtmf decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 4.2. oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 4.3. digital programmable gain/attenuat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.4. slic control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 22 4.5. fsk control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 24 5. pin descriptions: si3210/11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 6. pin descriptions: si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8. package outline: 38-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9. package outline: 38-pi n tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10. package outline: 16-pi n esoic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
si3210/si3211 4 rev. 1.45 1. electrical specifications table 1. absolute maximum ratings and thermal information 1 parameter symbol value unit si3210/11 dc supply voltage v ddd , v dda1 , v dda2 ?0.5 to 6.0 v input current, digital input pins i in 10 ma digital input voltage v ind ?0.3 to (v ddd +0.3) v operating temperature range 2 t a ?40 to 100 c storage temperature range t stg ?40 to 150 c tssop-38 thermal resistance, typical ? ja 70 c/w qfn-38 thermal re sistance, typical ? ja 35 c/w continuous power dissipation 2 p d 0.7 w si3201 dc supply voltage v dd ?0.5 to 6.0 v battery supply voltage v bat ?104 v input voltage: tip, ring, sringe, stipe pins v inhv (v bat ? 0.3) to (v dd + 0.3) v input voltage: itipp, itipn, iringp, iringn pins v in ?0.3 to (v dd + 0.3) v operating temperature range 2 t a ?40 to 100 c storage temperature range t stg ?40 to 150 c soic-16 thermal resistance, typical 3 ? ja 55 c/w continuous power dissipation 2 p d 0.8 at 70 c w 0.6 at 85 c notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specifie d in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. operation above 125 c junction temp erature may degrade device reliability. 3. thermal resistance assumes a multi-layer pcb with the exposed pad soldered to a topside pcb pad.
si3210/si3211 rev. 1.45 5 table 2. recommended operating conditions parameter symbol test condition min * typ max * unit ambient temperature t a k-grade 0 25 70 c ambient temperature t a b-grade ?40 25 85 c si3210/11 supply voltage v ddd ,v dda1 , v dda2 3.13 3.3/5.0 5.25 v si3201 supply voltage v dd 3.13 3.3/5.0 5.25 v si3201 battery voltage v bat v bath =v bat ?96 ? ?10 v *note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise stated. product specifications are only guaranteed for the typica l application circuit (including component tolerances). table 3. ac characteristics (v dda , v ddd = 3.13 to 5.25 v, t a = 0 to 70 c for k-grade, ?40 to 85 c for b-grade) parameter test condition min typ max unit tx/rx performance overload level thd = 1.5% 2.5 ? ? v pk single frequency distortion 1 2-wire ? pcm or pcm ? 2-wire: 200 hz?3.4 khz ???45db signal-to-(noise + distortion) ratio 2 200 hz to 3.4 khz d/a or a/d 8-bit active off-hook, and oht, any zac figure 1 ? ? audio tone generator signal-to-distortion ratio 2 0 dbm0, active off-hook, and oht, any zac 45 ? ? db intermodulation distortion ? ? ?45 db gain accuracy 2 2-wire to pcm, 1014 hz ?0.5 0 0.5 db pcm to 2-wire, 1014 hz ?0.5 0 0.5 db gain accuracy over frequency figure 3,4 ? ? group delay over frequency figure 5,6 ? ? gain tracking 3 1014 hz sine wave, reference level ?10 dbm signal level: 3 to ?37 db ?0.25 ? 0.25 db ?37 to ?50 db ?0.5 ? 0.5 db ?50 to ?60 db ?1.0 ? 1.0 db round-trip group delay at 1000 hz ? 1100 ? s gain step accuracy ?6 to +6 db ?0.017 ? 0.017 db
si3210/si3211 6 rev. 1.45 gain variation with temperature all gain settings ?0.25 ? 0.25 db gain variation with supply v dda =v dda = 3.3/5 v 5% ?0.1 ? 0.1 db 2-wire return loss 200 hz to 3.4 khz 30 35 ? db transhybrid balance 300 hz to 3.4 khz 30 ? ? db noise performance idle channel noise 4 c-message weighted ? ? 15 dbrnc psophometric weighted ? ? ?75 dbmp 3 khz flat ? ? 18 dbrn psrr from vdda rx and tx, dc to 3.4 khz 40 ? ? db psrr from vddd rx and tx, dc to 3.4 khz 40 ? ? db psrr from vbat rx and tx, dc to 3.4 khz 40 ? ? db longitudinal performance longitudinal to metallic or pcm balance 200 hz to 3.4 khz, ? q1,q2 ? 150, 1% mismatch 56 60 ? db ? q1,q2 ? 60 to 240 5 43 60 ? db ? q1,q2 ? 300 to 800 5 53 60 ? db using si3201 53 60 ? db metallic to longitudinal balance 200 hz to 3.4 khz 40 ? ? db longitudinal impedance 200 hz to 3.4 khz at tip or ring register selectable etbo/etba 00 01 10 ? ? ? 33 17 17 ? ? ? ? ? ? longitudinal current per pin active off-hook 200 hz to 3.4 khz register selectable etbo/etba 00 01 10 ? ? ? 4 8 12 ? ? ? ma ma ma notes: 1. the input signal level should be 0 dbm0 for frequencies greater than 100 hz. for 100 hz and below, the level should be ?10 dbm0. the output signal magnitude at any other frequ ency will be smaller than the maximum value specified. 2. analog signal measured as v tip ? v ring . assumes ideal line impedance matching. 3. the quantization errors inherent in the /a-law compand ing process can generate slightly worse gain tracking performance in the signal range of 3 to ?37 db for signal frequencies that are integer divisors of the 8 khz pcm sampling rate. 4. the level of any unwanted tones within the bandwid th of 0 to 4 khz does not exceed ?55 dbm. 5. assumes normal distribution of betas. table 3. ac characteristics (v dda , v ddd = 3.13 to 5.25 v, t a = 0 to 70 c for k-grade, ?40 to 85 c for b-grade) parameter test condition min typ max unit
si3210/si3211 rev. 1.45 7 figure 1. transmit and receive path sndr figure 2. overload compression performance 123456789 1 2 3 4 5 6 7 8 9 0 2.6 acceptable region fundamental input power (dbm0) fundamental output power (dbm0)
si3210/si3211 8 rev. 1.45 figure 3. transmit path frequency response typical response typical response
si3210/si3211 rev. 1.45 9 figure 4. receive path frequency response
si3210/si3211 10 rev. 1.45 figure 5. transmit group delay distortion figure 6. receive group delay distortion
si3210/si3211 rev. 1.45 11 table 4. linefeed characteristics (v dda , v ddd = 3.13 to 5.25 v, t a = 0 to 70c for k-grade, ?40 to 85c for b-grade) parameter symbol test condition min typ max unit loop resistance range* r loop see *note. 0 ? 160 ? dc loop current accuracy i lim = 29 ma, etba = 4 ma ?10 ? 10 % dc open circuit voltage accuracy active mode; v oc =48v, v tip ? v ring ?4 ? 4 v dc differential output resistance r do i loop < i lim ?160? ? dc open circuit voltage? ground start v octo i ring si3210/si3211 12 rev. 1.45 table 5. monitor adc characteristics (v dda , v ddd = 3.13 to 5.25 v, t a = 0 to 70 c for k-grade, ?40 to 85 c for b-grade) parameter symbol test condition min typ max unit differential nonlinearity (6-bit resolution) dnle ?1/2 ? 1/2 lsb integral nonlinearity (6-bit resolution) inle ?1 ? 1 lsb gain error (voltage) ? ? 10 % gain error (current) ? ? 20 % table 6. si321x dc characteristics, v dda =v ddd =5.0v (v dda ,v ddd = 4.75 to 5.25 v, t a = 0 to 70 c for k-grade, ?40 to 85 c for b-grade) parameter symbol test condition min typ max unit high level input voltage v ih 0.7 x v ddd ??v low level input voltage v il ??0.3xv ddd v high level output voltage v oh dio1,dio2,sdithru: i o = ?4 ma sdo, dtx:i o =?8ma v ddd ? 0.6 ? ? v dout: i o =?40ma v ddd ? 0.8 ? ? v low level output voltage v ol dio1,dio2,dout,sdithru: i o =4ma sdo,int ,dtx:i o =8ma ??0.4v input leakage current i l ?10 ? 10 a table 7. si321x dc characteristics, v dda =v ddd =3.3v (v dda ,v ddd = 3.13 to 3.47 v, t a = 0 to 70 c for k-grade, ?40 to 85 c for b-grade) parameter symbol test condition min typ max unit high level input voltage v ih 0.7 x v ddd ?? v low level input voltage v il ??0.3xv ddd v high level output voltage v oh dio1,dio2,sdithru: i o =?2 ma sdo, dtx:i o =?4ma v ddd ? 0.6 ? ? v dout: i o = ?40 ma v ddd ? 0.8 ? ? v low level output voltage v ol dio1,dio2,dout,sdithru: i o =2ma sdo,int ,dtx:i o =4ma ??0.4v input leakage current i l ?10 ? 10 a
si3210/si3211 rev. 1.45 13 table 8. power supply characteristics (v dda , v ddd = 3.13 to 5.25 v, t a = 0 to 70 c for k-grade, ?40 to 85 c for b-grade) parameter symbol test condition typ 1 typ 2 max unit power supply current, analog and digital i a + i d sleep (reset = 0) 0.1 0.13 0.3 ma open 33 42.8 49 ma active on-hook etbo = 4 ma, codec and gm ampli- fier powered down 37 53 68 ma active oht etbo = 4 ma 57 72 83 ma active off-hook etba = 4 ma, i lim =20ma 738899 ma ground start 36 47 55 ma ringing sinewave, ren = 1, v pk =56v 45 55 65 ma v dd supply current (si3201) i vdd sleep mode, reset = 0 100 100 ? a open (high impedance) 100 100 ? a active on-hook standby 110 110 ? a forward/reverse active off-hook, no i loop , etbo = 4 ma, v bat =?24v 11?ma forward/reverse oht, etbo = 4 ma, v bat =?70v 11?ma v bat supply current 3 i bat sleep (reset =0) 0 0 ? ma open (dcof = 1) 0 0 ? ma active on-hook v oc = 48 v, etbo = 4 ma 3 3 ? ma active oht etbo = 4 ma 11 11 ? ma active off-hook etba = 4 ma, i lim =20ma 30 30 ? ma ground start 2 2 ? ma ringing: v pk_ring = 56 v pk , sinewave ringing: ren = 1 5.5 5.5 ? ma v bat supply slew rate when using si3201 ? ? 10 v/s notes: 1. v ddd , v dda =3.3v. 2. v ddd , v dda =5.25v. 3. i bat = current from v bat (the large negative supply). for a switched-mode power supply regulator efficiency of 71%, the user can calculate the regulator current consumption as i bat x v bat /(0.71 x v dc ).
si3210/si3211 14 rev. 1.45 table 9. switching characteristics (general inputs) v dda =v dda = 3.13 to 5.25 v, t a = 0 to 70 c for k-grade, ?40 to 85 c for b-grade, c l =20pf) parameter symbol min typ max unit rise time, reset t r ?? 20ns reset pulse width t rl 100 ? ? ns note: all timing (except rise and fall time) is referenced to th e 50% level of the waveform. input test levels are v ih =v d ? 0.4 v, v il = 0.4 v. rise and fall times are referenced to the 20% and 80% levels of the waveform.
si3210/si3211 rev. 1.45 15 figure 7. spi timing diagram table 10. switching characteristics (spi) v dda =v dda = 3.13 to 5.25 v, t a = 0 to 70 c for k-grade, ?40 to 85 c for b-grade, c l =20pf parameter symbol test conditions min typ max unit cycle time sclk t c 0.062 ? ? s rise time, sclk t r ? ? 25 ns fall time, sclk t f ? ? 25 ns delay time, sclk fall to sdo active t d1 ? ? 20 ns delay time, sclk fall to sdo transition t d2 ? ? 20 ns delay time, cs rise to sdo tri-state t d3 ? ? 20 ns setup time, cs to sclk fall t su1 25 ? ? ns hold time, cs to sclk rise t h1 20 ? ? ns setup time, sdi to sclk rise t su2 25 ? ? ns hold time, sdi to sclk rise t h2 20 ? ? ns delay time between chip selects (continuous sclk) t cs 440 ? ? ns delay time between chip selects (non-continuous sclk) t cs 220 ? ? ns sdi to sdithru propagation delay t d4 ? 4 10 ns note: all timing is referenced to the 50% level of the waveform. input test levels are v ih =v ddd ?0.4 v, v il =0.4v sclk cs sdi t h1 t d3 sdo t d1 t d2 t su1 t r t r t c t su2 t h2 t cs t thru
si3210/si3211 16 rev. 1.45 figure 8. pcm highway interface timing diagram table 11. switching characteristics?pcm highway serial interface v d = 3.13 to 5.25 v, t a = 0 to 70 c for k-grade, ?40 to 85 c for b-grade, c l =20pf parameter symbol test conditions min 1 typ 1 max 1 units pclk frequency 1/t c ? ? ? ? ? ? ? ? 0.256 0.512 0.768 2 1.024 1.536 2 2.048 4.096 8.192 ? ? ? ? ? ? ? ? mhz mhz mhz mhz mhz mhz mhz mhz pclk duty cycle tolerance t dty 40 50 60 % pclk-to-fsync jitter tolerance t jitter ?120 ? 120 ns rise time, pclk t r ??25ns fall time, pclk t f ??25ns delay time, pclk rise to dtx active t d1 ??20ns delay time, pclk rise to dtx transition t d2 ??20ns delay time, pclk rise to dtx tri-state 3 t d3 ??20ns setup time, fsync to pclk fall t su1 25 ? ? ns hold time, fsync to pclk fall t h1 20 ? ? ns setup time, drx to pclk fall t su2 25 ? ? ns hold time, drx to pclk fall t h2 20 ? ? ns notes: 1. all timing is referenced to the 50% level of the waveform. input test levels are v ih ? v i/o ? 0.4v, v il =0.4v. 2. not a valid pclk frequency for gci mode. 3. specification applies to pclk fall to dtx tri-state when that mode is selected (tri = 0). pclk drx fsync dtx t d1 t d2 t su2 t h2 t d3 t r t c t su1 t h1 t f
si3210/si3211 rev. 1.45 17 figure 9. si3210/si3210m application circuit using si3201 si3201 4 si3210/si3210m 5 r15 243 c2 10 ? f c1 10 ? f r14 40.2k c5 22nf c6 22nf itipn iringn itipp iringp stipe sringe itipn iringn itipp iringp stipe sringe tip ring gnd vbat tip ring iref capp capm igmp igmn qgnd sclk sdi sdo cs fsync pclk drx dtx spi bus pcm bus int reset r5 200k r28 1 r21 15 vdd protection circuit c24 0.1 ? f c19 4.7 ? f r6 4.02k r7 4.02k vbath svbat 29 25 28 26 17 19 18 1 3 4 5 15 13 16 14 11 10 8 7 38 37 36 1 6 3 4 5 2 7 24 22 11 12 14 13 q9 2n2222 c26 0.1 ? f r29 1 vcc vcc sdcl sdch dc-dc converter circuit dcdrv dcff vdc vbat vdc sdcl sdch dcdrv dcff stipdc stipac r26 2 10 k gnd r32 2 10k vcc note 2 note 1 9 8 34 33 c18 4.7 ? f r1 200k 15 20 c3 220 nf r8 470 r3 200k 21 16 c4 220 nf r9 470 sringac sringdc notes: 1. values and configurations for these components can be derived from table 19 or from ?an45: design guide for the si3210 dc-dc converter?. 2. only one component per system needed. 3. all circuit ground should have a single-point connection to the ground plane. 4. si3201 bottom-side exposed pad should be electrically and thermally connected to bulk ground plane. 5. pin numbers for tssop shown. r2 196k r4 196k vddd vdda1 gndd gnda vdda2 31 23 test 32 10 27 30 47 h l2 vcc c15 0.1 f c16 0.1 f c17 10 f c31 c30 10 f 0.1 f
si3210/si3211 18 rev. 1.45 table 12. si3210/si3210m + si3201 external component values component(s) value package supplier c1,c2 10 f, 6 v ceramic or 16 v low leakage electrolytic, 20% radial murata, nichicon url1c100md c3,c4 220 nf, 100 v, x7r, 20% 1812 mur ata, johanson, novacap, venkel c5,c6 22 nf, 100 v, x7r, 20% 1206 mur ata, johanson, novacap, venkel c15,c16,c17,c24 0.1 f, 6 v, y5v, 20% 60 3 murata, johanson, novacap, venkel c18,c19 4.7 f, ceramic, 6 v, x7r, 20% 120 6 murata, johanson, novacap, venkel c26 0.1 f, 100 v, x7r, 20% 1210 mur ata, johanson, novacap, venkel c30,c31 10 f, 10 v, electrolytic, 20% radial panasonic l2 47 h, 150 ma smd coilcraft r1 1 ,r3 1 ,r5 1 200 k ? , 1/10 w, 1% 805 r2 1 ,r4 1 196 k ? , 1/10 w, 1% 805 r6,r7 4.02 k ? , 1/10 w, 1% 805 r8,r9 470 ? , 1/10 w, 1% 805 r14 40.2 k ? , 1/10 w, 1% 805 r15 243 ? , 1/10 w, 1% 805 r21 15 ? , 1/4 w, 5% 805 r26 2 10 k ? , 1/10 w, 1% 805 r28,r29 1/10 w, 1% (see ?an45: design guide for the si3210 dc-dc converter? or table 19 for value selection) 805 r32 2 10 k ? , 1/10 w, 5% 805 q9 60 v, general purpose switching npn sot-23 on semi mmbt2222alt1; central semi cmpt2222a; zetex fmmt2222 notes: 1. these resistors must be in an 0805 or larger package. 2. only one component per system needed.
si3210/si3211 rev. 1.45 19 figure 10. si3210 bjt/inductor dc-dc converter circuit q8 2n2222 c9 10 f r19 1 r20 1 r18 1 r17 f1 gnd l1 vbat c14 2 0.1 f vdc note 1 note 1 si3210 notes: 1. values and configurations for these components can be derived from ?an45: design guide for the si3210 dc-dc converter? or table 21. 2. voltage rating for c14 and c25 must be greater than vdc. c25 2 10 f c10 0.1 f r16 200 d1 es1d q7 fzt953 dcdrv dcff sdcl sdch
si3210/si3211 20 rev. 1.45 table 13. si3210 bjt/inductor dc-dc converter component values component(s) value package supplier c9 10 f, 100 v, electrolytic, 20% radial panasonic c10 0.1 f, 50 v, x7r, 20% 1210 murata, johanson, novacap, venkel c14* 0.1 f, x7r, 20% 1210 mura ta, johanson, novacap, venkel c25* 10 f, electrolytic, 20% radial panasonic r16 200 ? , 1/10 w, 5% 805 r17 1/10 w, 5% (see an45 or table 21 for value selection) 805 r18 1/4 w, 5% (see an45 or table 21 for value selection) 1206 r19,r20 1/10 w, 1% (see an45 or table 21 for value selection) 805 f1 fuse smd belfuse ssq series d1 ultra fast recovery 200 v, 1a rectifier do214- aa general semi es1d; central semi cmr1u-02 l1 1 a, shielded inductor (see an45 or table 21 for value selection) smd api delevan spd127 series, sumida cdrh127 series, datatronics dr340- 1 series, coilcraft ds5022, tdk slf12565 q7 120 v, high current switching pnp sot-223 zetex fzt953, fzt955, ztx953, ztx955; sanyo 2sa1552 q8 60 v, general purpose switching npn sot-23 on semi mmbt2222alt1, mps2222a; central semi cmpt2222a; zetex fmmt2222 *note: voltage rating of this device must be greater than v dc .
si3210/si3211 rev. 1.45 21 figure 11. si3210m mosfet/transformer dc-dc converter circuit table 14. si3210m mosfet/transformer dc-dc converter component values component(s) value package supplier c9 10 f, 100 v, electrolyt ic, 20% radial panasonic c14* 0.1 f, x7r, 20% 1210 murata, johanson, novacap, venkel c25* 10 f, electrolytic, 20% radial panasonic c27 470 pf, 100 v, x7r, 20% 1206 murata, johanson, novacap, venkel r17 200 k ? , 1/10 w, 5% 805 r18 1/4 w, 5% (see ?an45: design guide for the si3210 dc-dc converter? or table 20 for value selection) 1206 r19,r20 1/10 w, 1% (see an45 or table 20 for value selection) 805 r22 22 ? , 1/10 w, 5% 805 f1 fuse smd belfuse ssq series d1 ultra fast recovery 200 v, 1 a rectifier d214-aa general semi es1d; central semi cmr1u-02 t1 power transformer smd coiltronic ctx01-15275; datatronics sm76315; midcom 31353r-02 m1 100 v, logic level input mosfet sot-223 intl rect. irll014n; intersil huf76609d3s; st micro std5ne10l, stn2ne10l *note: voltage rating of this device must be greater than v dc . d1 es1d c9 10 f c25 2 10 f r19 1 r20 1 r18 1 r22 22 r17 200 k f1 sdch sdcl dcff dcdrv gnd vbat c14 2 0.1 f vdc c27 470 pf m1 irll014n t1 1 nc note 1 note 1 1 2 3 4 10 notes: 1. values and configurations for these components can be derived from an45 or table 20. 2. voltage rating for c14 and c25 must be greater than vdc. si3210m 6
si3210/si3211 22 rev. 1.45 figure 12. si3211 typical application circuit using si3201 si3201 3 si3211 4 r15 243 c2 10 ? f c1 10 ? f r14 40.2k c5 22 nf c6 22 nf itipn iringn itipn iringn tip ring vbat tip ring iref capp capm igmp igmn qgnd sclk sdi sdo cs fsync pclk drx dtx spi bus pcm bus int reset r5 200k protection circuit r6 4.02k r7 4.02k vbath svbat sringac sringdc 29 25 28 26 17 19 18 1 3 4 5 16 14 11 10 38 37 36 1 6 3 4 5 2 7 24 22 11 12 14 13 dio2 dio1 dcsw dout stipdc stipac r26 1 10k r32 1 10k vcc note 1 9 8 34 33 nc itipp iringp stipe sringe itipp iringp stipe sringe nc nc gnd vdd c24 0.1 ? f c19 4.7 ? f 15 13 8 7 vcc c18 4.7 ? f notes: 1. only one component per system needed. 2. all circuit grounds should have a single- point connection to the ground plane. 3. si3201 bottom-side exposed pad should be electrically and thermally connected to bulk ground plane. 4. pin numbers for tssop shown. r3 200k 21 16 c4 220 nf r9 470 r1 200k 15 20 c3 220 nf r8 470 r18 1.8k q8 5551 vbath gnd q7 5401 vbatl d1 4003 r16 200k r2 196k r4 196k gnd 0.1 f c9 vddd vdda1 gndd gnda vdda2 31 23 test 32 10 27 30 47 h l2 vcc c15 0.1 f c16 0.1 f c17 10 f c31 c30 10 f 0.1 f
si3210/si3211 rev. 1.45 23 table 15. si3211 + si3201 external component values component(s) value package supplier c1,c2 10 f, 6 v ceramic or 16 v, low-leakage electrolytic, 20% radial murata, nichicon url1c100md c3,c4 220 nf, 100 v, x7r, 20% 1812 murata, johanson, novacap, venkel c5,c6 22 nf, 100 v, x7r, 20% 1206 murata, johanson, novacap, venkel c9 0.1 f, 100 v, x7r, 20% 1210 murata, johanson, novacap, venkel c15,c16,c17,c24 0.1 f, 6 v, y5v, 20% 1 206 murata, johanson, novacap, venkel c18,c19 4.7 f ceramic, 6 v, x7r, 20% 1 206 murata, johanson, novacap, venkel c30,c31 10 f, 10 v, electrolytic, 20% radial panasonic l2 47 h, 150 ma smd coilcraft d1 200 v, 1 a rectifier melf on semi: mra4003, in4003 q7 120 v, pnp, bjt sot-89 on semi: 2n5401 q8 120 v, npn, bjt sot-223 on semi: 2n5551 r1 1 ,r3 1 ,r5 1 ,r16 1 200 k ? , 1/10 w, 1% 805 r2 1 ,r4 1 196 k ? , 1/10 w, 1% 805 r6,r7 4.02 k ? , 1/10 w, 1% 805 r8,r9 470 ? , 1/10 w, 1% 805 r14 40.2 k ? , 1/10 w, 1% 805 r15 243 ? , 1/10 w, 1% 805 r18 1.8 k ? , 1/10 w, 5% 805 r26 2 10 k ? , 1/10 w, 1% 805 r32 2 10 k ? , 1/10 w, 5% 805 notes: 1. these resistors must be in an 0805 or larger package. 2. only one component per system needed.
si3210/si3211 24 rev. 1.45 figure 13. si3210/si3210m typical application circuit using discrete components notes: 1. values and configurations for these compo- nents can be derived from table 19 or from ?an45: design guide for the si3210 dc-dc converter?. 2. only one component per system needed. 3. all circuit grounds should have a single-point connection to the ground plane. 4. optional components to improve idle channel noise. 5. the trace resistance between r6 and c26 should equal the trace resistance between r7 and c26. 6. pin numbers for tssop shown. si3210/si3210m 6 r15 243 c2 10uf c1 10uf r14 40.2k c5 22nf c6 22nf itipp itipn stipe iringp iringn sringe r1 200k r3 200k tip ring iref capp capm igmp igmn qgnd sclk sdi sdo cs fsync pclk drx dtx spi bus pcm bus int reset r28 1 r21 15 protection circuit r2 100k 15 20 28 29 17 26 25 19 18 21 16 38 37 36 1 6 3 4 5 2 7 24 22 11 12 14 13 q9 2n2222 r29 1 vcc sdcl sdch dc-dc converter circuit dcdrv dcff vdc vbat vdc sdcl sdch dcdrv dcff stipdc stipac r26 2 10k gnd r32 2 10k vcc note 2 note 1 9 8 34 33 r7 80.6 c7 220nf q5 5551 q3 5401 q2 5401 r11 10 r12 5.1k r6 80.6 c8 220nf q6 5551 q4 5401 q1 5401 r10 10 r13 5.1k gnd c4 220nf r9 470 sringac sringdc c3 220nf r8 470 svbat r102 (100k) c32 4 c26 0.1 f r4 100k 0.1 f r104 (100k) r5 100k 0.1 f r105 (100k) 0.1 f c34 4 c33 4 vddd vdda1 gndd gnda vdda2 31 23 test 32 10 27 30 47 h l2 vcc c15 0.1 f c16 0.1 f c17 10 f c31 c30 10 f 0.1 f
si3210/si3211 rev. 1.45 25 table 16. si3210/si3210m external component values?discrete solution component(s) value package supplier/part number c1,c2 10 f, 6 v ceramic or 16 v low-leakage electrolytic, ? 20% radial murata, panasonic, nichicon url1c100md c3,c4 220 nf, 100 v, x7r, ? 20% 1812 murata, johanson, novacap, venkel c5,c6 22nf, 100v, x7r, ? 20% 1206 murata, johanson, novacap, venkel c7,c8 220 nf, 50 v, x7r, ? 20% 1812 murata, johanson, novacap, venkel c15,c16,c17 0.1 f, 6 v, y5v, ? 20% 603 murata, johanson, novacap, venkel c26 0.1 f, 100 v, x7r, ? 20% 1210 murata, johanson, novacap, venkel c30,c31 10 f, 10 v, electrolytic, 20% radial panasonic c32,c33,c34 0.1 f, 50 v, 20% 805 venkel l2 47 h, 150 ma smd coilcraft q1,q2,q3,q4 120 v, pnp, bjt sot-23 central semi cmpt5401; on semi mmbt5401lt1, 2n5401; zetex fmmt5401; fairchild 2n5401; samsung 2n5401 q5,q6 120 v, npn, bjt sot-223 central semi czt5551, on semi 2n5551; fairchild 2n5551; phillips 2n5551 q9 npn general purpose bjt sot-23 on semi mmbt2222alt1, mps2222a; central semi cmpt2222a; zetex fmmt2222 r1 1 , r3 1 200 k ? , 1/10 w, ? 1% 805 r2 1 , r4 1 , r5 1 , r102 1 , r104 1 , r105 1 100 k ? , 1/10 w, 1% 805 r6,r7 80.6 ? , 1/4 w, ? 1% 1210 r8,r9 470 ? , 1/10 w, ? 1% 805 r10,r11 10 ? , 1/10 w, ? 5% 805 r12,r13 5.1 k ? , 1/10 w, ? 5% 805 r14 40.2 k ? , 1/10 w, ? 1% 805 r15 243 ? , 1/10 w, ? 1% 805 r21 15 ? , 1/4 w, ? 1% 805 r26 2 10 k ? , 1/10 w, 1% 805 r28,r29 1/10 w, ? 1% (see ?an45: design guide for the si3210/15/16 dc-dc converter? or table 19 for value selection) 805 r32 2 10 k ? , 1/10 w, ? 5% 805 notes: 1. these resistors must be in 0805 or larger package. 2. only one component per system needed.
si3210/si3211 26 rev. 1.45 figure 14. si3211 typical application circuit using discrete solution si3211 5 r15 243 c2 10uf c1 10uf r14 40.2k iref capp capm igmp igmn qgnd sclk sdi sdo cs fsync pclk drx dtx spi bus pcm bus int reset 38 37 36 1 6 3 4 5 2 7 24 22 11 12 14 13 dio2 dio1 dcsw dout r26 1 10k r32 1 10k vcc note 1 9 8 34 33 nc nc nc c5 22nf c6 22nf r1 200k r3 200k tip ring r18 1.8k protection circuit r2 100k r4 100k 15 20 28 29 17 26 25 19 18 21 16 q8 5551 vbath gnd notes: 1. only one component per system needed. 2. all circuit grounds should have a single-point connection to the ground plane. 3. the trace resistance between r6 and c26 should equal the trace resistance between r7 and c26. 4. optional components to improve idle channel noise. 5. pin numbers for tssop shown. r7 80.6 c7 220nf q5 5551 q3 5401 q2 5401 r11 10 r12 5.1k r6 80.6 c8 220nf q6 5551 q4 5401 q1 5401 r10 10 r13 5.1k gnd c4 220nf r9 470 c3 220nf r8 470 q7 5401 vbatl d1 4003 r16 200k itipp itipn stipe iringp iringn sringe stipdc stipac sringac sringdc svbat r105 (100k) c33 4 0.1f r5 100k r104 (100k) c34 4 0.1f r102 (100k) c32 4 0.1f c26 0.1 f vddd vdda1 gndd gnda vdda2 31 23 test 32 10 27 30 47 h l2 vcc c15 0.1 f c16 0.1 f c17 10 f c31 c30 10 f 0.1 f
si3210/si3211 rev. 1.45 27 table 17. si3211 external component values?discrete solution component(s) value package supplier/part number c1,c2 10 f, 6 v ceramic or 16 v low leakage electrolytic, ? 20% radial murata, panasonic, nichicon url1c100md c3,c4 220 nf, 100 v, x7r, ? 20% 1812 murata, johanson, novacap, venkel c5,c6 22nf, 100v, x7r, ? 20% 1206 murata, johanson, novacap, venkel c7,c8 220 nf, 50 v, x7r, ? 20% 1812 murata, johanson, novacap, venkel c9 0.1 f, 100 v, x7r, ? 20% 1210 panasonic c15,c16,c17 0.1 f, 6 v, y5v, ? 20% 603 murata, johanson, novacap, venkel c30,c31 10 f, 10 v, x7r, 20% radial panasonic c32, c33, c34 0.1 f, 50 v, x7r, 20% 805 venkel l2 47 h, 150 ma smd coilcraft r1 1 ,r3 1 ,r16 1 200 k ? , 1/10 w, ? 1% 805 r2 1 , r4 1 , r5 1 , r102 1 , r104 1 , r105 1 100 k ? , 1/10 w, 1% 805 r6,r7 80.6 ? , 1/4 w, ? 1% 1210 r8,r9 470 ? , 1/10 w, ? 1% 805 r10,r11 10 ? , 1/10 w, ? 5% 805 r12,r13 5.1 k ? , 1/10 w, ? 5% 805 r14 40.2 k ? , 1/10 w, ? 1% 805 r15 243 ? , 1/10 w, ? 1% 805 r18 1.8 k ? , 1/10 w, ? 5% 805 r26 2 10 k ? , 1/10 w, 1% 805 r32 2 10 k ? , 1/10 w, ? 5% 805 d1 200 v 1a rectifier melf on semi mra4003, 1n4003 q1,q2,q3,q4,q7 120 v, pnp, bjt sot-23 central semi cmpt5401; on semi mmbt5401lt1, 2n5401; zetex fmmt5401 q5,q6 120 v, npn, bjt sot-223 central semi czt5551, on semi 2n5551 q8 120 v, npn, bjt sot-223 central semi cmpt5551, on semi 2n5551 notes: 1. these resistors must be in an 0805 or larger package. 2. only one component per system needed.
si3210/si3211 28 rev. 1.45 figure 15. si321x optional equivalent q5, q6 bias circuit the subcircuit above can be s ubstituted into any of the proslic solutions as an optional bias circuit for q5 and q6. for this optional subcircuit, c7 and c8 differ in voltage and capacitance from the standard circuit. r23 and r24 are additional components. r7 80.6 rre c7 100 nf crbn q4 5401 qtdn c8 ctbn 100 nf q5 5551 qrp r23 3.0k rrbn0 r24 3.0k rtbn0 q3 5401 qrdn r6 80.6 rte r12 5.1k rrbn r13 5.1k rtbn q6 5551 qtn table 18. si321x optional bias component values component value package supplier/part number c7,c8 100 nf, 100 v, x7r, ? 20% 1210 murata, johanson, venkel r23,r24 3.0 k ? , 1/10 w, ? 5% 805 table 19. component value selection for si3210/si3210m component value package comments r28 1/10 w, 1% resistor for v dd = 3.3 v: 26.1 k ? for v dd = 5.0 v: 37.4 k ? 805 r28 = (v dd + v be )/148 a where v be is the nomi nal vbe for q9 r29 1/10 w, 1% resistor for v clamp = 80 v: 541 k ? for v clamp = 85 v: 574 k ? for v clamp =100v: 676k ? 805 r29 = v clamp /148 a where v clamp is the clamping voltage for v bat
si3210/si3211 rev. 1.45 29 table 20. component value selection examples for si3210m mosfet/transformer dc-dc converter vdc maximum ringing load/loop resistance transformer ratio r18 r19, r20 3.3 v 3 ren/117 ? 1?2 0.06 ? 7.15 k ? 5.0 v 5 ren/117 ? 1?2 0.10 ? 16.5 k ? 12 v 5 ren/117 ? 1?3 0.6 ? 56.2 k ? 24 v 5 ren/117 ? 1?4 2.1 ? 121 k ? note: there are other system and software conditions that influence component value selection. refer to ?an45: design guide for the si3210 dc-dc converter? for detailed guidance. table 21. component value selection examples for si3210 bjt/inductor dc-dc converter vdc maximum ringing load/loop resistance l1 r17 r18 r19, r20 5 v 3 ren/117 ? 67 h 150 ? 0.15 ? 16.5 k ? 12 v 5 ren/117 ? 150 h 162 ? 0.56 ? 56.2 k ? 24 v 5 ren/117 ? 220 h 175 ? 2.0 ? 121 k ? note: there are other system and soft ware conditions that influe nce component value selection. refer to ?an45: design guide for the si3210 dc-dc converter? for detailed guidance.
si3210/si3211 30 rev. 1.45 2. functional description the proslic ? is a single, low-voltage cmos device that provides all the slic, codec, dtmf detection, and signal generation functions needed for a complete analog telephone interface. the proslic performs all battery, overvoltage, ringing, supervision, codec, hybrid, and test (borscht) function s. unlike most monolithic slics, the si3210 does not require externally-supplied high-voltage battery supplies. instead, it generates all necessary battery voltages from a positive dc supply using its own dc-dc converter controller. two fully- programmable tone generators can produce dtmf tones, phase continuous fsk (caller id) signaling, and call progress tones. dtmf decoding and pulse metering signal generation are also integrated. the si3201 linefeed interface ic performs all high-voltage functions. as an option, the si3201 can also be replaced with low- cost discrete components as shown in the typical application circuits in figures 12, 13, and 14. the proslic is ideal for shor t loop applications, such as terminal adapters, cable telephony, pbx/key systems, wireless local loop (wll), and voice over ip solutions. the device meets all relevant lssgr and ccitt standards. the linefeed provides programmable on-hook voltage, programmable off-hook loop current, reverse battery operation, loop or ground start operation, and on-hook transmission ringing voltage. loop current and voltage are continuously monitored using an integrated a/d converter. balanced 5 ren ringing with or without a programmable dc offset is integrated. the available offset, frequency, waveshape, and cadence options are designed to ring the widest variety of terminal devices and to reduce external controller requirements. a complete audio transmit and receive path is integrated, including dtmf decoding, ac impedance, and hybrid gain. these features are software- programmable, allowing for a single hardware design to meet international requir ements. digital voice data transfer occurs over a st andard pcm bus. control data is transferred using a standard spi. the device is available in a 38-pin qfn or tssop package. 2.1. linefeed interface the proslic?s linefeed interface offers a rich set of features and programmable flexibility to meet the broadest applications requirements. the dc linefeed characteristics are software-programmable. key current, voltage, and power measurements are acquired in real time and provided in software registers. 2.1.1. dc feed characteristics the proslic has programmable constant voltage and constant current zones as shown in figure 16. open- circuit tip-to-ring voltage (v oc ) defines the constant voltage zone and is programmable from 0 v to 94.5 v in 1.5 v steps. the loop current limit (i lim ) defines the constant current zone and is programmable from 20 ma to 41 ma in 3 ma steps. the proslic has an inherent dc output resistance (r o ) of 160 ? . figure 16. simplified dc current/voltage linefeed characteristic the tip-to-ring voltage (v oc ) is offset from ground by a programmable voltage (v cm ) to provide voltage headroom to the positive-mos t terminal (tip in forward polarity states and ring in reverse polarity states) for carrying audio signals. table 22 summarizes the parameters to be initialized before entering an active state. table 22. programmable ranges of dc linefeed characteristics parameter programmable range default value register bits location* i lim 20 to 41 ma 20 ma ilim[2:0] direct register 71 v oc 0 to 94.5 v 48 v voc[5:0] direct register 72 v cm 0 to 94.5 v 3 v vcm[5:0] direct register 73 *note: the proslic uses registers that are both directly and indirectly mapped. a ?direct? register is one that is mapped directly. v (tip-ring) (v) v oc constant voltage zone r o =160 ? constant current zone i lim i loop (ma)
si3210/si3211 rev. 1.45 31 2.1.2. linefeed architecture the proslic is a low-volt age cmos device that uses either an si3201 linefeed interface ic or low-cost external components to control the high voltages required for subscriber line interfaces. figure 17 is a simplified illustration of the linefeed control loop circuit for tip or ring and the external components used. the proslic uses both voltage and current sensing to control tip and ring. dc and ac line voltages on tip and ring are measured through sense resistors r dc and r ac . the proslic uses linefeed transistors q p and q n to drive tip and ring. q dn isolates the high-voltage base of q n from the proslic. the proslic measures voltage at various nodes in order to monitor the linefeed current. r dc , r se , and r bat provide access to these measuring points. the sense circuitry is calibrated on-chip to guarantee measurement accuracy with standard external component tolerances. see "2.1.9. linefeed calibration" on page 36 for details. 2.1.3. linefeed operation states the proslic linefeed has eight states of operation as shown in table 23. the state of operation is controlled using the linefeed control register (direct register 64). the open state turns off all currents into the external bipolar transistors and can be used in the presence of fault conditions on the line and to generate open switch intervals (osis). tip and ring are effectively tri-stated with a dc output impedance of about 150 k ? . the proslic can also automatically enter the open state if it detects excessive power being consumed in the external bipolar transistors. see ?2.1.5. power monitoring and line fault detection? for more details. in the forward active and re verse active states, linefeed circuitry is on, and the audio signal paths are powered down. in the forward and reverse on-hook transmission states, audio signal paths are powered up to provide data transmission during an on-hook loop condition. the tip open state turns off all control currents to the external bipolar devices connected to tip and provides an active linefeed on ring for ground start operation. the ring open state provides similar operation with the ring drivers off and tip active. the ringing state drives programmable ringing waveforms onto the line. 2.1.4. loop voltage and current monitoring the proslic continuously monitors the tip and ring voltages and external bjt currents. these values are available in registers 78?89. table 24 on page 33 lists the values that are measured and their associated registers. an internal a/d converter samples the measured voltages and currents from the analog sense circuitry and translates them into the digital domain. the a/d updates the samples at a rate of 800 hz. two derived values are also reported: loop voltage and loop current. the loop voltage, v tip ?v ring , is reported as a 1-bit sign, 6-bit magnitude format. for ground start operation, the reported value is the ring voltage. the loop current, (i q1 ? i q2 + i q5 ?i q6 )/2, is reported in a 1- bit sign, 6-bit magnitude format. in ring open and tip open states, the loop current is reported as (i q1 ? i q2 ) + (i q5 ?i q6 ).
si3210/si3211 32 rev. 1.45 figure 17. simplified proslic linefeed architecture for tip and ring leads (one shown) table 23. proslic linefeed operations lf[2:0]* linefeed state description 000 open tip and ring tri-stated 001 forward active v tip > v ring 010 forward on-hook transmission v tip > v ring ; audio signal paths powered on 011 tip open tip tri-stated, ring active; used for ground start 100 ringing ringing waveform applied to tip and ring 101 reverse active v ring > v tip 110 reverse on-hook transmission v ring > v tip ; audio signal paths powered on 111 ring open ring tri-stated, tip active note: the linefeed register (lf) is located in direct register 64. dsp a/d d/a d/a a/d dc control ac control dc control loop ac control loop battery sense emitter sense dc sense r dc r se r bat q dn q p q n r e v bat tip or ring r bp r ac c ac ac sense audio codec monitor a/d slic dac on-chip external components ? si3201
si3210/si3211 rev. 1.45 33 2.1.5. power monitoring and line fault detection in addition to reporting voltages and currents, the proslic continuously monito rs the power dissipated in each external bipolar transistor. real-time output power of any one of the six linefee d transistors can be read by setting the power monitor pointer (direct register 76) to point to the desired transistor and then reading the line power output monitor (direct register 77). the real-time power measurements are low-pass filtered and compared to a maximum power threshold. maximum power thresholds and filter time constants are software-programmable and should be set for each transistor pair based on the characteristics of the transistors used. table 25 describes the registers associated with this function. if the power in any external transistor exceeds the programmed threshold, a power alarm event is triggered. the proslic sets the power alarm register bit, generates an interrupt (if enabled), and automatically enters the open state (if aopn = 1). this feature protects the external transistors from fault conditions and, combined with the loop voltage and current monitors, allows diagnosis of the type of fault condition present on the line. the value of each thermal lo w-pass filter pole is set according to the equation: where ? is the thermal time c onstant of the transistor package, 4096 is the full range of the 12-bit register, and 800 is the sample rate in hertz. generally ? = 3 seconds for sot223 packages and ? = 0.16 seconds for sot23, but check with the manufacturer for the package thermal constant of a specif ic device. for example, the power alarm threshold and low-pass filter values for q5 and q6 using a sot223 package transistor are computed as follows: thus, indirect register 34 should be set to 150dh. note: the power monitor resolution for q3 and q4 is different from that of q1, q2, q5, and q6. table 24. measured real-time linefeed interface characteristics parameter measurement range resolution register bits location* loop voltage sense (v tip ? v ring ) ?94.5 to +94.5 v 1.5 v lvsp, lvs[6:0] direct register 78 loop current sense ?78.75 to +78.5 ma 1.25 ma lcsp, lcs[5:0] direct register 79 tip voltage sense 0 to ?95.88 v 0 .376 v vtip[7:0] direct register 80 ring voltage sense 0 to ?95.88 v 0 .376 v vring[7:0] dir ect register 81 battery voltage sense 1 (v bat ) 0 to ?95.88 v 0.376 v vbats1[7:0] direct register 82 battery voltage sense 2 (v bat ) 0 to ?95.88 v 0.376 v vbats2[7:0] direct register 83 transistor 1 current sense 0 to 81.3 5 ma 0.319 ma iq1[7:0] direct register 84 transistor 2 current sense 0 to 81.3 5 ma 0.319 ma iq2[7:0] direct register 85 transistor 3 current sense 0 to 9.59 ma 37.6 a iq3[7:0] direct register 86 transistor 4 current sense 0 to 9.59 ma 37.6 a iq4[7:0] direct register 87 transistor 5 current sense 0 to 80.5 8 ma 0.316 ma iq5[7:0] direct register 88 transistor 6 current sense 0 to 80.5 8 ma 0.316 ma iq6[7:0] direct register 89 *note: the proslic uses registers that are both directly and indirectly mapped. a ?direct? register is one that is mapped directly. thermal lpf register 4096 800 ? ? ------------------ 2 3 ? = ppt56 p max resolution ------------------------------- 2 7 ? 1.28 0.0304 ----------------- - 2 7 ? 5389 150dh ====
si3210/si3211 34 rev. 1.45 table 25. associated power monitoring and power fault registers parameter description/ range resolution register bits location* power monitor pointer 0 to 5 points to q1 to q6, respectively n/a pwrmp[2:0] direct register 76 line power monitor outp ut 0 to 7.8 w for q1, q2, q5, q6 0 to 0.9 w for q3, q4 30.4 mw 3.62 mw pwrom[7:0] direct register 77 power alarm threshold, q1 & q2 0 to 7. 8 w 30.4 mw ppt12[7:0] indirect register 32 power alarm threshold, q3 & q4 0 to 0. 9 w 3.62 mw ppt34[7:0] indirect register 33 power alarm threshold, q5 & q6 0 to 7. 8 w 30.4 mw ppt56[7:0] indirect register 34 thermal lpf pole, q1 & q2 see equation above. nq12[7:0] indirect register 37 thermal lpf pole, q3 & q4 see equation above. nq34[7:0] indirect register 38 thermal lpf pole, q5 & q6 see equation above. nq56[7:0] indirect register 39 power alarm interrupt pending bits 2 to 7 correspond to q1 to q6, respec- tively n/a qnap[n+1], where n = 1 to 6 direct register 19 power alarm interrupt enable bits 2 to 7 correspond to q1 to q6, respec- tively n/a qnae[n+1], where n = 1 to 6 direct register 22 power alarm automatic/manual detect 0 = manual mode 1 = enter open state upon power alarm n/a aopn direct register 67 *note: the proslic uses registers that are both directly and indirectly mapped. a ?direct? register is one that is mapped directly. an ?indirect? register is one that is accessed us ing the indirect access registers (direct registers 28 through 31).
si3210/si3211 rev. 1.45 35 figure 18. loop closure detection 2.1.6. loop closure transition detection a loop closure transition ev ent signals that the terminal equipment has gone from on-hook to off-hook or from off-hook to on-hook; detection occurs while the proslic linefeed is in its on-hook transmission or active states. the proslic performs loop closure detection digitally using its on-chip monitor a/d converter. the functional blocks required to implement loop closure detection are shown in figure 18. the prim ary input to the system is the loop current sense value provided in the lcs register (direct register 79). the lcs value is processed in the input signal processor when the proslic is in the on-hook transmission or active linefeed state, as indicated by the linefeed shadow register, lfs[2:0] (direct register 64). the data then feeds into a programmable di gital low-pass filter, which removes unwanted ac signal components before threshold detection. the output of the low-pass filter is compared to a programmable threshold, lcrt (indirect register 28). the threshold comparator output feeds a programmable debouncing filter. the outpu t of the debouncing filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, lcdi (direct register 69). if the debounce interval has been satisfied, the lcr bit will change state to indicate that a valid loop closure transition has occurred. a loop closure transition interrupt is generated if enabled by the lcie bit (direct register 22). table 26 lists the registers that must be written or monitored to correctly detect a loop closure condition. 2.1.7. loop closure threshold hysteresis silicon revisions c and high er support t he addition of programmable hysteresis to the loop closure threshold, which can be enabled by setting hysten = 1 (direct register 108, bit 0). the hysteresis is defined by lcrt (indirect register 28) and lcrtl (indirect register 43), which set the upper and lower bounds, respectively. 2.1.8. voltage-based loop closure detection silicon revisions c and higher also support an optional voltage-based loop closure detection mode, which is enabled by setting lcve = 1 (direct register 108, bit 2). in this mode, the loop voltage is compared to the loop closure threshold register (lcrt), which represents a minimum voltage threshold instead of a maximum current threshold. if hysteresis is also enabled, lcrt represents the upper voltage boundary, and lcrtl represents the lower voltage boundary for hysteresis. although voltage-based loop closure detection is an option, the default current-based loop closure detection is recommended. isp_out nclr lcdi input signal processor digital lpf loop closure threshold debounce filter + ? lcr lcip lcie interrupt logic lcs lvs lcve lfs lcrtl lcrt hysten table 26. register set for loop closure detection parameter register location loop closure interrupt pending lcip direct reg. 19 loop closure interrupt enable lcie direct reg. 22 loop closure thresh- old lcrt[5:0] indirect reg. 28 loop closure threshold?lower lcrtl[5:0] indirect reg. 43 loop closure filter coefficient nclr[12:0] indirect reg. 35 loop closure detect status (monitor only) lcr direct reg. 68 loop closure detect debounce interval lcdi[6:0] direct reg. 69 hysteresis enable hysten direct reg. 108 voltage-based loop closure lcve direct reg. 108
si3210/si3211 36 rev. 1.45 2.1.9. linefeed calibration an internal calibration algorithm corrects for internal and external component errors. the calibration is initiated by setting the cal bit in direct register 96. upon completion of the calibration cycle, this bit is automatically reset. it is recommended that a calibration be executed following system powerup. upon release of the chip reset, the si3210 will be in the open state. the calibration can be initiated after powering up the dc-dc converter and allowing it to settle for time (t settle ). additional calibrations may be performed, but only one calibration should be necessary as long as the system remains powered up. during calibration, v bat , v tip , and v ring voltages are controlled by the calibration engine to provide the correct external voltage conditions for the algorithm. calibration should be performed in the on-hook state. ring or tip must not be connected to ground during the calibration. when using the si3201, automatic calibration routines for ring gain mismatch and tip gain mismatch should not be performed. instead of running these two calibrations automatically, fo llow the instructions for manual calibration in ?an35: si321x user?s quick reference guide?. 2.2. battery voltage generation and switching the proslic supports two modes of battery supply operation. first, the si3210 integrates a dc-dc converter controller that dynamically regulates a single output voltage. this mode eliminat es the need to supply large external battery voltages. instead, it converts a single positive input voltage into the real-time battery voltage needed for any given state according to programmed linefeed parameters. second, the si3211 supports switching between high and low battery voltage supplies, as would a trad itional monolithic slic. for single to low channel count applications, the si3210 proves to be an economical choice, as the dc-dc converter eliminates the need to design and build high- voltage power supplies. for higher channel count applications where centralized battery voltage supply is economical or for modular legacy systems where battery voltage is already available, the si3211 is recommended. 2.2.1. dc-dc converter general description (si3210/si3210m only) the dc-dc converter dynamically generates the large negative voltages required to operate the linefeed interface. the si3210 acts as the controller for a buck- boost dc-dc converter that converts a positive dc voltage into the desired negative battery voltage. in addition to eliminating external power supplies, this allows the si3210 to dynamically control the battery voltage to the minimum required for any given mode of operation. two different dc-dc circuit options are offered: a bjt/ inductor version and a mosfet/transformer version. due to the differences on the driving circuits, there are two different versions of the si3210. the si3210 supports the bjt/inductor circuit option, and the si3210m version supports the mosfet solution. the only difference between the two versions is the polarity of the dcff pin with respect to the dcdrv pin. for the si3210, dcdrv and dcff are of opposite polarity. for the si3210m, dcdrv and dcff are the same polarity. table 27 summarizes these differences. extensive design guidance on each of these circuits can be obtained from ?an45: design guide for the si3210 dc-dc converter? and from an interactive dc-dc converter design spreadsheet. both of these documents are available on the silicon laboratories website (www.silabs.com). 2.2.2. bjt/inductor circuit option using si3210 the bjt/inductor circuit opt ion shown in figure 10 on page 19 offers a flexible, low-cost solution. depending on selected l1 inductance value and the switching frequency, the input voltage (v dc ) can range from 5 v to 30 v. because of the nature of a dc-dc converter?s operation, peak and average input currents can become large with small input volt ages. consider this when selecting the appropriate input voltage and power rating for the v dc power supply. for this solution, a pnp power bjt (q7) switches the current flow through low esr inductor l1. the si3210 uses the dcdrv and dcff pins to switch q7 on and off. dcdrv controls q7 th rough npn bjt q8. dcff is ac-coupled to q7 through capacitor c10 to assist r16 in turning off q7. therefore, dcff must have opposite polarity to dcdrv, and the si3210 (not si3210m) must be used. table 27. si3210 and si3210m differences device dcff signal polarity dcpol si3210 = dcdrv 0 si3210m = dcdrv 1 notes: 1. dcff signal polarity with respect to dcdrv signal. 2. direct register 93, bit 5; this is a read-only bit.
si3210/si3211 rev. 1.45 37 2.2.3. mosfet/transforme r circuit option using the si3210m the mosfet/transformer circuit option (shown in figure 11 on page 21) offers higher power efficiencies across a larger input voltage range. depending on the transformer?s primary inductor value and the switching frequency, the input voltage (v dc ) can range from 3.3 v to 35 v. therefore, it is possible to power the entire proslic solution from a single 3.3 v or 5 v power supply. by nature of a dc-dc converter?s operation, peak and average input currents can become large with small input voltages. consider this when selecting the appropriate input voltage and power rating for the v dc power supply (number of ren supported). for this solution, an n-channel power mosfet (m1) switches the current flow through a power transformer, t1. t1 is specified in ?a n45: design guide for the si3210 dc-dc converter? and includes several taps on the primary side to facilit ate a wide range of input voltages. the si3210m version of the si3210 must be used for the application circuit depicted in figure 11 because the dcff pin is used to drive m1 directly and, therefore, must be the same polarity as dcdrv. dcdrv is not used in this circuit option; connecting dcff and dcdrv together is not recommended. 2.2.4. dc-dc conver ter architecture (si3210/si3210m only) the control logic for a pulse-width-modulated (pwm) dc-dc converter is incorporated in the si3210. output pins dcdrv and dcff are used to switch a bipolar transistor or mosfet. the polarity of dcff is opposite that of dcdrv. the dc-dc converter circuit is powered on when the dcof bit in the powerd own register (direct register 14, bit 4) is cleared to 0. the switching regulator circuit within the si3210 is a high- performance, pulse-width modulation controller. the control pins are driven by the pwm controller logic in the si3210. the regulated output voltage (v bat ) is sensed by the svbat pin and is used to detect whether the output voltage is above or below an internal reference for the desired battery voltage. the dc monitor pins, sdch and sdcl, monitor input current and voltage to the dc-dc converter external circuitry. if an overload condition is detected, the pwm controller will turn off the swit ching transistor for the remainder of a pwm period to prevent damage to external components. it is important that the proper value of r18 be selected to ensu re safe operation. guidance is given in an45. the pwm controller operates at a frequency set by the dc-dc converter pwm register (direct register 92). during a pwm period, the outputs of the control pins, dcdrv and dcff, are asserted for a time given by the read-only pwm pulse width register (direct register 94). the dc-dc converter must be off for some time in each cycle to allow the inductor or transformer to transfer its stored energy to the output capacitor, c9. this minimum off time can be set through the dc-dc converter switching delay register, (direct register 93). the number of 16.384 mhz clock cycles that the controller is off is equal to dctof (bits 0 through 4) plus 4. if the dc monitor pins detect an overload condition, the dc-dc converter interrupts its conv ersion cycles regardless of the register settings to prevent component damage. these inputs should be calib rated by writing the dccal bit (bit 7) of the dc-dc converter switching delay register, direct register 93, after the dc-dc converter has been turned on. because the si3210 dynamically regulates its own battery supply voltage using the dc-dc converter controller, the battery voltage, v bat , is offset from the negative-most terminal by a programmable voltage, v ov , to allow voltage headroom for carrying audio signals. as mentioned previously, the si3210 dynamically adjusts v bat to suit the particular circuit requirement. to illustrate this, th e behavior of v bat in the active state is shown in figure 19. in the active state, the tip-to-ring open circuit voltage is kept at v oc in the constant voltage region while the regulator output voltage v bat =v cm + v oc + v ov . when the loop current attempts to exceed i lim , the dc line driver circuit enters constant current mode allowing the tip to ring voltage to track r loop . as the tip terminal is kept at a constant voltage, it is the ring terminal voltage that tracks r loop and, as a result, the |v bat | voltage will also track r loop . in this state, |v bat |=i lim x r loop + v cm +v ov . as r loop decreases below the voc/i lim mark, the regulator output voltage can continue to track r loop (track = 1), or the r loop tracking mechanism is stopped when |v bat |=|v batl | (track = 0). the former case is the more common application and provides the maximum power dissipation savings. in principle, the regulator output voltage can go as low as |v bat |=v cm + v ov , offering significant power savings. when track = 0, |v bat | will not decrease below v batl . the ring terminal voltage, however, continues to decrease with decreasing r loop .
si3210/si3211 38 rev. 1.45 the power dissipation on the npn bipolar transistor driving the ring terminal can become large and may require a higher power rating device. the non-tracking mode of operation is requi red by specific terminal equipment that, in order to initiate certain data transmission modes, goes briefly on-hook to measure the line voltage to determine whether there is any other off-hook terminal equipment on the same line. track = 0 mode is desired since the regulator output voltage has long settling time constants (on the order of tens of milliseconds) and cannot change rapidly for track = 1 mode. therefore, the brief on-hook voltage measurement would yield approximately the same voltage as the off-hook line voltage and cause the terminal equipment to incorrectly sense another off- hook terminal. figure 19. v tip , v ring , and v bat in the forward active state constant i region constant v region v oc i lim v cm v oc v ov v ov v ring v bat v batl r loop v v tip t r a c k = 1 track=0 |v tip - v ring | table 28. associated relevant dc-dc converter registers parameter range resolution register bit location dc-dc converter power-off control n/a n/a dcof direct register 14 dc-dc converter calibration enable/status n/a n/a dccal direct register 93 dc-dc converter pwm period 0 to 15.564 s 61.035 ns dcn[7:0] direct register 92 dc-dc converter min. off time (0 to 1.892 s) + 4 ns 61.035 ns dctof[4:0] direct register 93 high battery voltage?v bath 0 to ?94.5 v 1.5 v vbath[5:0] direct register 74 low battery voltage?v batl 0 to ?94.5 v 1.5 v vbatl[5:0] direct register 75 v ov 0 to ?9 v or 0 to ?13.5 v 1.5 v vmind[3:0] vov indirect register 41 direct register 66 note: the proslic uses registers that are both directly and indirectly mapped. a ?dir ect? register is one that is mapped directly. an ?indirect? register is one that is accessed us ing the indirect access registers (direct registers 28 through 31).
si3210/si3211 rev. 1.45 39 2.2.5. dc-dc converter enhancements silicon revisions c an d higher support two enhancements to the dc-dc converter. the first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. this option is enabled by setting dcsu = 1 (direct register 108, bit 5). the second enhancement is an audio band filter that removes audio band noise from the dc-dc converter control loop. this option is enabled by setting dcfil = 1 (direct register 108, bit 1). 2.2.6. dc-dc converter during ringing when the proslic enters the ringing state, it requires voltages well above those used in the active mode. the voltage to be generated and regulated by the dc-dc converter during a ringing burst is set using the v bath register (direct register 74). v bath can be set between 0 and ?94.5 v in 1.5 v steps. to avoid clipping the ringing signal, v bath must be set larger than the ringing amplitude. at the end of each ringing burst, the dc-dc converter adjusts back to active state regulation as described above. 2.2.7. external battery switching (si3211 only) the si3211 supports switching between two battery voltages. the circuit for external battery switching is defined in figure 14. typically, a high-voltage battery (e.g., ?70 v) is used for on-hook and ringing states, and a low-voltage battery (e.g., ?24 v) is used for the off- hook condition. the proslic uses an external transistor to switch between the two supplies. when the proslic changes operating states, it automatically switches batter y supplies if the automatic/ manual control bit, abat (direct register 67, bit 3), is set. for example, the proslic will switch from high battery to low battery when it detects an off-hook event through either a ring trip or loop closure event. if automatic battery selection is disabled (abat = 0), the battery is selected by the battery feed select bit, batsl (direct register 66, bit 1). silicon revisions c and higher support the option to add a 60 ms debounce period to the battery switching circuit when transitioning from high battery to low battery. this option is enabled by setting swdb = 1 (direct register 108, bit 3). this debounce minimizes battery transitions in the case of pulse dialing or other quick on- hook to off-hook transitions. 2.3. tone generation two digital tone generators are provided in the proslic. they allow the generation of a wide variety of single- or dual-tone frequency and amplitude combinations and spare the user the effort of generating the required pots signaling tones on the pcm highway. dtmf, fsk (caller id), call progress, and other tones can all be generated on-chip. the tones can be sent to either the receive or transmit paths (see figure 25 on page 49). 2.3.1. tone generator architecture a simplified diagram of the tone generator architecture is shown in figure 20. the oscillator, active/inactive timers, interrupt block, and signal routing block are connected to give the user flexibility in creating audio signals. control and status register bits are placed in the figure to indicate their association with the tone generator architecture. these registers are described in more detail in table 29.
si3210/si3211 40 rev. 1.45 figure 20. simplified tone generator diagram 2.3.2. oscillator frequency and amplitude each of the two tone generators contains a two-pole resonate oscillator circ uit with a programmable frequency and amplitude, which are programmed via indirect registers osc1 , osc1x, osc1y, osc2, osc2x, and osc2y. the sample rate for the two oscillators is 8000 hz. the equations are as follows: coeff n =cos(2 ?? f n /8000 hz), where f n is the frequency to be generated; oscn = coeff n x(2 15 ); where desired vrms is the amplitude to be generated; oscny = 0, n = 1 or 2 for oscillator 1 or oscillator 2, respectively. for example, in order to generate a dtmf digit of 8, the two required tones are 852 hz and 1336 hz. assuming the generation of half-scale values (ignoring twist) is desired, the following values are calculated: osc1y = 0 osc2 = 0.49819 (2 15 ) = 16324 = 3fc4h osc2y = 0 the above computed values would be written to the corresponding registers to in itialize the oscillators. once the oscillators are initializ ed, the oscilla tor control registers can be accessed to enable the oscillators and direct their outputs. 2.3.3. tone generator cadence programming each of the two tone genera tors contains two timers, one for setting the active period and one for setting the inactive period. the oscillato r signal is g enerated during the active period and su spended during the inactive period. both the active and inactive periods can be programmed from 0 to 8 seconds in 125 s steps. the active period time interval is set using oat1 (direct registers 36 and 37) for tone generator 1 and oat2 (direct registers 40 and 41) for tone generator 2. to enable automatic cadence for tone generator 1, define the oat1 and oit1 registers and then set the o1tae bit (direct register 32, bit 4) and o1tie bit (direct register 32, bit 3). this enables each of the timers to control the state of the oscillator enable bit, o1e (direct register 32, bi t 2). the 16-bit counter will begin counting until the active timer expires, at which ozn ossn *tone generator 1 only n = "1" or "2" for tone generator 1 and 2, respectively two-pole resonance oscillator 16-bit modulo counter oatn oitn oitne oatne oscn oscny oscnx load logic zero cross logic signal routing onso to tx path to rx path int logic onip onie int logic onap onae rel* register load enable 8 khz clock zero cross one oat expire oit expire 8 khz clock oscnx 1 4 -- - 1 coeff ? 1 coeff + ----------------------- - ? 2 15 1 ? ?? ? desired v rms 1.11 v rms ------------------------------------- ? = coeff 1 2 ? 852 8000 ---------------- - ?? ?? cos 0.78434 == osc1 0.78434 2 15 ?? 25701 6465h = == osc1x 1 4 -- - 0.21556 1.78434 --------------------- ? 2 15 1 ? ?? ? 0.5 ? 1424 590h = = = coeff 2 2 ? 1336 8000 -------------------- ?? ?? cos 0.49819 == osc2x 1 4 -- - 0.50181 1.49819 --------------------- ? 2 15 1 ? ?? ? 0.5 ? 2370 942h = = =
si3210/si3211 rev. 1.45 41 time the 16-bit counter will reset to zero and begin counting until the inactive timer expires. the cadence continues until the user clears the o1tae and o1tie control bits. the zero crossing detect feature can be implemented by setting the oz1 bit (direct register 32, bit 5). this ensures that each oscillator pulse ends without a dc component. the timing diagram in figure 21 is an example of an output cadence using the zero crossing feature. one-shot oscillation can be achieved by enabling o1e and o1tae. direct control over the cadence can be achieved by controlling the o1e bit (direct register 32, bit 2) directly if o1tae and o1tie are disabled. the operation of tone generato r 2 is identical to that of tone generator 1 using its respective control registers. note: tone generator 2 should not be enabled simultane- ously with the ringing oscillator due to resource sharing within the hardware. continuous phase frequency-shift keying (fsk) waveforms may be created using tone generator 1 (not available on tone generato r 2) by setting the rel bit (direct register 32, bit 6), which enables reloading of the osc1, osc1x, and osc1y registers at the expiration of the active timer, oat1. table 29. associated tone generator registers tone generator 1 parameter description / range register bits location oscillator 1 frequency coeffici ent sets oscillator frequency osc1 [15:0] indirect register 13 oscillator 1 amplitude coefficient sets oscilla tor amplitude osc1x[15:0 ] indirect register 14 oscillator 1 initial phase coefficient sets in itial phase osc1y[15:0] indirect register 15 oscillator 1 active timer 0 to 8 sec onds oat1[15:0] direct registers 36 & 37 oscillator 1 inactive timer 0 to 8 sec onds oit1[15:0] direct register 38 & 39 oscillator 1 control status and control registers oss1, rel, oz1, o1tae, o1tie, o1e, o1so[1:0] direct register 32 tone generator 2 parameter description/ra nge register location oscillator 2 frequency coeffici ent sets oscillator frequency osc2 [15:0] indirect register 16 oscillator 2 amplitude coefficient sets oscilla tor amplitude osc2x[15:0 ] indirect register 17 oscillator 2 initial phase coefficient sets in itial phase osc2y[15:0] indirect register 18 oscillator 2 active timer 0 to 8 sec onds oat2[15:0] direct registers 40 & 41 oscillator 2 inactive timer 0 to 8 sec onds oit2[15:0] direct register 42 & 43 oscillator 2 control status and control registers oss2, oz2, o2tae, o2tie, o2e, o2so[1:0] direct register 33
si3210/si3211 42 rev. 1.45 figure 21. tone generator timing diagram 2.3.4. enhanced fsk waveform generation silicon revisions c and hi gher support enhanced fsk generation capabilities, which can be enabled by setting fsken = 1 (direct register 108, bit 6) and ren = 1 (direct register 32, bit 6). in this mode, the user can define mark (1) and space (0) attributes once during initialization by defining indirect registers 99?104. the user need only indicate 0-to-1 and 1-to-0 transitions in the information stream. by wr iting to fskdat (direct register 52), this mode applies a 24 khz sample rate to tone generator 1 to give addi tional resolution to timers and frequency generation. ?an32: si321x frequency shift keying (fsk) modulation? gives detailed instructions on how to im plement fsk in this mode. additionally, sample source code is available from silicon laboratori es upon request. 2.3.5. tone generator interrupts both the active and inactive timers can generate their own interrupt to signal ?on/off? transitions to the software. the timer interrupts for tone generator 1 can be individually enabled by setting the o1ae and o1ie bits (direct register 21, bits 0 and 1, respectively). timer interrupts for tone generator two are o2ae and o2ie (direct register 21, bits 2 and 3, respectively). a pending interrupt for each of the timers is determined by reading the o1ap, o1ip, o2ap, and o2ip bits in the interrupt status 1 register (direct register 18, bits 0 through 3, respectively). 2.4. ringing generation the proslic provides fully-programmable internal balanced ringing with or without a dc offset to ring a wide variety of terminal devices. all parameters associated with ringing (ringing frequency, waveform, amplitude, dc offset, and ringing cadence) are software- programmable. both sinusoidal and trapezoidal ringing waveforms are supported, and the trapezoidal crest factor is programmable. ringing signals of up to 88 v peak or more can be generated, enabling the proslic to drive a 5 ren (1380 ? + 40 f) ringer load across loop lengths of 2000 feet (160 ? ) or more. 2.4.1. ringing architecture the ringing generator architecture is nearly identical to that of the tone generator. the sinusoidal ringing waveform is generated using an internal two-pole resonance oscillator circuit with programmable frequency and amplitude. however, since ringing frequencies are very low compared to the audio band signaling frequencies, the ringing waveform is generated at a rate of 1 khz instead of 8 khz. the ringing generator has tw o timers that function the same as the tone generator timers. they allow on/off cadence settings of up to 8 seconds on and 8 seconds off. in addition to contro lling ringing cadence, these timers control the transition into and out of the ringing state. table 30 summarizes t he list of registers used for ringing generation. note: tone generator 2 should not be enabled concurrently with the ringing generator due to resource sharing within the hardware. ... ... 0,1 ... 0,1 ... ... , oat1 ... , oat1 ... , oit1 0,1 ... 0,1 ... o1e oss1 tone gen. 1 signal output
si3210/si3211 rev. 1.45 43 when the ringing state is invoked by writing lf[2:0] = 100 (direct regist er 64), the proslic will go into the ringing state and start the first ring. at the expiration of rat, the proslic will turn off the ringing waveform and will go to the on-hook transmission state. at the expiration of rit, ringing will again be initiated. this process will continue as l ong as the two timers are enabled and the linefeed control register is set to the ringing state. 2.4.2. sinusoidal ringing to configure the proslic for sinusoidal ringing, the frequency and amplitude are in itialized by writing to the following indirect regist ers: rco, rngx, and rngy. the equations for rco, rngx, rngy are as follows: where and f = desired ringing frequency in hertz. the minimum allowed peak tip-to-ring ringing voltage depends on the linefeed state. in the forward active linefeed state, the selected ringing amplitude (rngx, indirect register 21) plus t he selected ringing dc voltage offset (roff, indirect register 19) must be greater than the selected on-hook line voltage setting (voc, direct register 72). in the reverse active linefeed state, the selected ringing amplitude (rngx, indirect register 21) minus the selected ringing dc voltage offset (roff, indirect register 19) must be greater than the selected on-hook line voltage setting (voc, direct register 72). using a 70 vpk 20 hz ringing signal as an example, the equations are as follows: table 30. registers for ringing generation parameter range/ de scription register bits location ringing waveform sine/trapezoid tsws direct register 34 ringing voltage offset enable enabled/ disabled rvo direct register 34 ringing active timer enable enabled/ disabled rtae direct register 34 ringing inactive timer enable enabled/ disabled rtie direct register 34 ringing oscillator enable enabled/ disabled roe direct register 34 ringing oscillator active ti mer 0 to 8 seconds rat[15:0] direct registers 48 and 49 ringing oscillator inactive timer 0 to 8 seconds rit[15:0] direct registers 50 and 51 linefeed control (initiates ringing state) ringing state = 100b lf[2:0] direct register 64 high battery voltage 0 to ?94.5 v vbath[5:0] direct register 74 ringing dc voltage offset 0 to 94.5 v roff[15:0] indirect register 19 ringing frequency 15 to 100 hz rco[15:0] indirect register 20 ringing amplitude 0 to 94.5 v rngx[15:0] indirect register 21 ringing initial phase sets initial phase for sinewave and period for trapezoid rngy[15:0] indirect register 22 common mode bias adjust during ringing 0 to 22.5 v vcmr[3:0] indirect register 40 note: the proslic uses registers that are both directly and indi rectly mapped. a ?direct? register is one that is mapped directly. an ?indirect? register is one that is accessed using the indirect acce ss registers (direct registers 28 through 31). rco coeff 2 15 ?? ? = coeff 2 ? f 1000 hz ---------------------- - ?? ?? cos = rngx 1 4 -- - 1coeff ? 1 coeff + ----------------------- - ? 2 15 ? desired v pk 0to94.5v ?? 96 v ----------------------------------------------------------------------- - ? = rngy 0 = coeff 2 ? 20 ? 1000 hz ---------------------- - ?? ?? 0.99211 = cos =
si3210/si3211 44 rev. 1.45 in addition, the user must select the sinusoidal ringing waveform by writing tsws = 0 (direct register 34, bit 0). 2.4.3. trapezoidal ringing in addition to the sinuso idal ringing waveform, the proslic supports trapezoidal ringing. figure 22 illustrates a trapezoidal ri nging waveform with offset v roff . figure 22. trapezoidal ringing waveform to configure the proslic for trapezoidal ringing, the user should follow the same basic procedure as in the sinusoidal ringing section, but using the following equations: rco is a value added or subtracted from the waveform to ramp the signal up or down in a linear fashion. this value is a function of rise time, period, and amplitude, where rise time and period are related through the following equation for the crest factor of a trapezoidal waveform. where t = ringing period, and cf = desired crest factor. for example, to generate a 71 v pk , 20 hz ringing signal, the equations are as follows: for a crest factor of 1.3 and a period of 0.05 seconds (20 hz), the rise time requirement is 0.0153 seconds. in addition, the user must select the trapezoidal ringing waveform by writing tsws = 1 in direct register 34. 2.4.4. ringing dc voltage offset a dc offset can be added to the ac ringing waveform by defining the offset voltage in roff (indirect register 19). the offset, v roff , is added to the ringing signal when rvo is set to 1 (direct register 34, bit 1). the value of roff is calculated as follows: 2.4.5. linefeed considerations during ringing care must be taken to keep the generated ringing signal within the ringing volt age rails (gnda and v bat ) to maintain proper biasing of the external bipolar transistors. if the ringing signal nears the rails, a distorted ringing signal and excessive power dissipation in the external transistors results. to prevent this invalid operation, set the v bath value (direct register 74) to a value higher than the maximum peak ringing voltage. the discussion below outlines the considerations and equations that govern the selection of the v bath setting for a particular desired peak ringing voltage. first, the required amount of ringing overhead voltage, v ovr , is calculated based on the maximum value of current through the load, i load,pk , the minimum current gain of q5 and q6, and a reasonable voltage required to keep q5 and q6 out of saturation. for ringing signals up to v pk =87v, v ovr = 7.5 v is a safe value. however, to determine v ovr for a specific case, use the equations below. rco 0.99211 2 15 ?? ? 32509 7efdh === rngx 1 4 -- - 0.00789 1.99211 --------------------- ? 2 15 ? 70 96 ------ ? 376 0177h = = = rngy 0 = time v roff t=1/freq t rise v tip-ring rngy 1 2 -- - period ? 8000 ? = rngx desired v pk 96 v ----------------------------------- 2 15 ?? ? = rco 2 rngx ? t rise 8000 ? --------------------------------- = t rise 3 4 -- - t1 1 cf 2 ---------- - ? ?? ?? = rngy 20 hz ?? 1 2 -- - 1 20 hz ---------------- ? 8000 ? 200 c8h = = = rngx 71 v pk ?? 71 96 ------ 2 15 ? 24235 5eabh = = = rco 20 hz , 1.3 crest factor ?? 2 24235 ? 0.0153 8000 ? ------------------------------------- - 396 018ch = = = roff v roff 96 ----------------- - 2 15 ? = i load , pk v ac , pk r load ------------------- i os + v ac , pk n ren 6.9 k ? ------------------ ? i os + ==
si3210/si3211 rev. 1.45 45 where: n ren is the ringing ren load (max value = 5), i os is the offset current flowing in the line driver circuit (max value=2ma), and v ac,pk = amplitude of the ac ringing waveform. it is good practice to provide a buffer of a few more milliamperes for i load,pk to account for possible line leakages, etc. the total i load,pk current should be smaller than 80 ma. where ? is the minimum expected current gain of transistors q5 and q6. the minimum value for v bath is therefore given by the following: the proslic is designed to create a fully-balanced ringing waveform, meaning that the tip and ring common mode voltage, (v tip + v ring )/2, is fixed. this voltage is referred to as vcm_ring and is automatically set to the following: vcmr is an indirect register, which provides the headroom by the ringing waveform with respect to the v bath rail. the value is set as a 4-bit setting in indirect register 40 with an lsb voltage of 1.5 v/lsb. register 40 should be set with the calculated v ovr to provide voltage headroom during ringing. silicon revisions c and high er support the option to briefly increase the maximum differential current limit between the voltage transition of tip and ring from ringing to a dc linefeed state. this mode is enabled by setting ilimen = 1 (direct register 108, bit 7). 2.4.6. ring trip detection a ring trip event signals that the terminal equipment has gone off-hook during the ringing state. the proslic performs ring trip detection digitally using its on-chip a/ d converter. the functional blocks required to implement ring trip detection are shown in figure 23. the primary input to the system is the loop current sense (lcs) value provided by the current monitoring circuitry and reported in direct register 79. lcs data is processed by the input signal processor when the proslic is in the ringing state as indicated by the linefeed shadow register (direct register 64). the data then feeds into a programmable digital low-pass filter that removes unwanted ac signal components before threshold detection. the output of the low-pass filter is compared to a programmable threshold, rptp (indirect register 29). the threshold comparator output feeds a programmable debouncing filter. the outpu t of the debouncing filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the ring trip debounce interval, rtdi[6:0] (direct register 70). if the debounce interval has been satisfied, the rtp bi t of direct register 68 will be set to indicate that a valid ring trip has occurred. a ring trip interrupt is generated if enabled by the rtie bit (direct register 22). table 31 lists the registers that must be written or monitor ed to correctly detect a ring trip condition. the recommended values for rptp, nrtp, and rtdi vary according to the programmed ringing frequency. register values for various ringing frequencies are given in table 32. figure 23. ring trip detector v ovr i load , pk ? 1 + ? ------------ - ? 80.6 ? 1v + ?? ? = vbath v ac , pk v roff v ovr ++ = vcm _ ring vbath vcmr ? 2 --------------------------------------------- - = lcs isp_out lfs nrtp rptp rtdi input signal processor digital lpf ring trip threshold debounce filter + ? rtp rtip rtie interrupt logic dbiraw
si3210/si3211 46 rev. 1.45 2.5. pulse me tering generation there is an additional tone generator suitable for generating tones above the audio frequency. this oscillator is provided for th e generation of billing tones that are typically 12 khz or 16 khz. the generator follows the same algorithm as described in "2.3. tone generation" on page 39 with the exception that the sample rate for computation is 64 khz instead of 8 khz. the equations are as follows: where full scale v rms =0.85v rms for a matched load. the initial phase of the pulse metering signal is set to 0 internally; so, there is no register to serve this purpose. the pulse metering generator timers and associated pulse metering timer registers are similar to those of the tone generators. these timers count 8 khz sample periods like the other tones even though the sinusoid is generated at 64 khz. table 31. associated registers for ring trip detection parameter register location ring trip interrupt pending rtip direct register 19 ring trip interrupt enable rtie direct register 22 ring trip detect debounce interv al rtdi[6:0] direct register 70 ring trip threshold rptp[5:0] indirect register 29 ring trip filter coefficient nrtp[12:0] indirect register 36 ring trip detect status (monit or only) rtp direct register 68 note: the proslic uses registers that are both directly and indirectly mapped. a ?direct? register is one that is mapped directly. an ?indirect? register is one that is accessed us ing the indirect access registers (direct registers 28 through 31). table 32. recommended ring trip values for ringing ringing frequency nrtp rptp rtdi hz decimal hex decimal hex decimal hex 16.667 64 0200 34 ma 3600 15.4 ms 0f 20 100 0320 34 ma 3600 12.3 ms 0b 30 112 0380 34 ma 3600 8.96 ms 09 40 128 0400 34 ma 3600 7.5 ms 07 50 213 06a8 34 ma 3600 5 ms 05 60 256 0800 34 ma 3600 4.8 ms 05 coeff 2 ? f 64000 hz -------------------------- ?? ?? cos = plsco coeff 2 15 1 ? ?? ? = plsx 1 4 -- - 1 coeff ? 1 coeff + ----------------------- - 2 15 1 ? ?? ? desired v rms full scale v rms ------------------------------------------- - ? =
si3210/si3211 rev. 1.45 47 the pulse metering oscilla tor has a volume envelope (linear ramp) on the on/off tr ansitions of the oscillator. the volume value is incremented by the value in the plsd register (indirect register 23) at an 8 khz rate. the sinusoidal generator ou tput is multiplied by this volume before being sent to the dac. the volume will ramp from 0 to 7fff in increments of plsd; so, the value of plsd will set the slope of the ramp. when the pulse metering signal is turn ed off, the vo lume will ramp to 0 by decrementing according to the value of plsd. figure 24. pulse metering volume envelope 2.6. dtmf detection the dual-tone multi-frequency (dtmf) tone signaling standard is also known as touch tone. it is an in-band signaling system used to replace the pulse-dial signaling standard. in dtmf, two tones are used to generate a dtmf digit. one tone is chosen from four possible row tones, and one tone is chosen from four possible column tones. the sum of these tones constitutes one of 16 possible dtmf digits. 2.6.1. dtmf detection architecture dtmf detection is performed using a modified goertzel algorithm to compute the dual frequency tone (dft) for each of the eight dtmf frequencies as well as their second harmonics. at the end of the dft computation, the squared magnitudes of the dft results for the eight dtmf fundamental tones are computed. the row results are sorted to determine the strongest row frequency; the column frequencies are sorted as well. at the completion of this process, a number of checks are made to determine whether the strongest row and column tones constitute a dtmf digit. the detection process is performed twice within the 45 ms minimum tone time. a digit must be detected on two consecutive tests following a pause to be recognized as a new digit. if all tests pass, an interrupt is generated, and the dtmf digit value is loaded into the dtmf register. if tones occur at the maximum rate of 100 ms per digit, the interrupt must be serviced within 85 ms so that the current digit is not overwritten by a new one. there is no buffering of the digit information. table 33. associated pulse metering generator registers parameter description / range register bits location pulse metering frequency coefficient sets oscillator frequency plsco[15:0] indirect register 25 pulse metering amplitude coefficient sets oscillator amplitude pl sx[15:0] indirect register 24 pulse metering attack/decay ramp rate 0 to plsx (full amplitude) plsd[15:0] indirect register 23 pulse metering active timer 0 to 8 seconds pat[15:0] direct registers 44 & 45 pulse metering inactive timer 0 to 8 se conds pit[15:0] direct register 46 & 47 pulse metering control status and control registers pstat, pmae, pmie, pmoe direct register 35 note: the proslic uses registers that are bot h directly and indirectly mapped. a direct register is one that is mapped directly. an indirect register is one that is accessed using the indirect access registers (direct registers 28 through 31). pulse metering oscillator volume +/? plsd to dac clip to 7fff or 0 8 khz x
si3210/si3211 48 rev. 1.45 2.7. audio path unlike traditional slics, the codec function is integrated into the proslic. the 16-bit codec offers programmable gain/attenuation blocks and several loopback modes. the signal path block diagram is shown in figure 25. 2.7.1. transmit path in the transmit path, the analog signal fed by the external ac coupling capacitors is amplified by the analog transmit amplifier, atx, prior to the a/d converter. the gain of the atx is user-selectable to one of mute/?3.5/0/3.5 db options. the main role of atx is to coarsely adjust the signal swing to be as close as possible to the full-scale in put of the a/d converter in order to maximize the signal-to-noise ratio of the transmit path. after passing through an anti-aliasing filter, the analog signal is processed by the a/d converter, producing an 8 khz, 16-bit wide, linear pcm data stream. the standard requirements for transmit path attenuation for signals above 3.4 khz are implemented as part of the combined decimation filter characteristic of the a/d converter. one more digital filter is available in the transmit path: thpf. thpf implements the high-pass attenuation requirements for signals below 65 hz. the linear pcm data stream output from thpf is amplified by the transmit-path programmable gain amplifier, adcg, which can be programmed from ? ? db to 6 db. the dtmf decoder can receive the linear pcm data stream at this point to perform the digit extraction when enabled by the user. the final step in transmit path signal processing is the user-selectable a-law or -law compression, which can reduce the data stream word width to 8 bits. depending on the pcm_mode register selection, every 8-bit compressed serial data word will occupy one time slot on the pcm highway, or every 16-bit uncompressed serial data word will occupy two time slots on the pcm highway.
si3210/si3211 rev. 1.45 49 + mute h from billing tone dac from billing tone dac atx + interpolation filter mute dacg ? /a-law compressor ? /a-law expander serial input decimation filter rhpf thpf dtmf decoder serial output digital rx digital tx dual tone generator full analog loopback adcg d/a + a/d hyba h txm digital loopback dlm alm1 analog loopback alm2 off chip on chip hybp transmit path tip ring xac rac g m i buf ? + arx rxm ? figure 25. ac signal path block diagram
si3210/si3211 50 rev. 1.45 2.7.2. receive path in the receive path, the optionally-compressed 8-bit data is first expanded to 16-bit words. the pcmf register bit can bypass the expansion process, in which case two 8-bit words are assembled into one 16- bit word. dacg is the rece ive path programmable gain amplifier, which can be programmed from ? ? db to 6 db. an 8 khz, 16-bit signal is then provided to a d/a converter. the resulting analog signal is amplified by the analog receive amplifier, arx, which is user- selectable to one of several options: mute, ?3.5, 0, or 3.5 db. it is then applied at the input of the transconductance amplifier (gm), which drives the off- chip current buffer (i buf ). 2.7.3. audio characteristics the dominant source of distortion and noise in both the transmit and receive paths is the quantization noise introduced by the -law or the a-law compression process. figure 1 on page 7 specifies the minimum signal-to-noise-and-distortion ratio for either path for a sine wave input of 200 hz to 3400 hz. both the -law and the a-la w speech encoding allow the audio codec to transfer and process audio signals larger than 0 dbm0 without clipping. the maximum pcm code is generated for a -law encoded sine wave of 3.17 dbm0 or an a-law encoded sine wave of 3.14 dbm0. the proslic overload clipping limits are driven by the pcm encoding process. figure 2 on page 7 shows the acceptable limits for the analog-to-analog fundamental power transfer-function, which bounds the behavior of proslic. the transmit path gain distortion versus frequency is shown in figure 3 on page 8. the same figure also presents the minimum required attenuation for any out- of-band analog signal that may be applied on the line. note the presence of a high-pass filter transfer function that ensures at least 30 db of attenuation for signals below 65 hz. the low-pass filter transfer function that attenuates signals above 3.4 khz has to exceed the requirements specified by the equations in figure 3 on page 8 and is implemented as part of the a-to-d converter. the receive path transfer function requirement, shown in figure 4 on page 9, is very similar to the transmit path transfer function. the most notable difference is the absence of the high-pass filt er portion. the only other differences are the maximum 2 db of attenuation at 200 hz (as opposed to 3 db for the transmit path) and the 28 db of attenuation for any frequency above 4.6 khz. the pcm data rate is 8 khz and, thus, no frequencies greater than 4 khz can be digitally encoded in the data stream. from this point of view, at frequencies greater than 4 khz, the plot in figure 4 should be interpreted as the maximum allowable magnitude of any spurious signals that are generated when a pcm data stream representing a sine wave signal in the range of 300 hz to 3.4 khz at a level of 0 dbm0 is applied at the digital input. the group delay distortion in either path is limited to no more than the levels indicated in figure 5 on page 10. the reference in figure 5 is the smallest group delay for a sine wave in the range of 500 hz to 2500 hz at 0dbm0. the block diagram for the voice-band signal processing paths is shown in figure 25. both the receive and transmit paths employ the optimal combination of analog and digital signal processing to provide maximum performance while offe ring sufficient flexibility to allow users to optimize for their particular proslic application. all programmable signal-processing blocks are indicated symbolically in figure 25 by a dashed arrow across them. the tw o-wire (tip/ring) voice- band interface to the proslic is implemented using a small number of external components. the receive path interface consists of a unity-gain current buffer, i buf , while the transmit path in terface is simply an ac coupling capacitor. signal paths, although implemented differentially, are shown as single-ended for simplicity. 2.7.4. transhybrid balance the proslic provides programmable transhybrid balance with gain block h. (see figure 25.) in the ideal case, where the synthesized slic impedance exactly matches the subscriber loop impedance, the transhybrid balance should be set to subtract a ?6 db level from the transmit path signal. the transhybrid balance gain can be adjusted from ?2.77 db to +4.08 db around the ideal setting of ?6 db by programming the hyba[2:0] bi ts of the hybrid control register (direct register 11). note that adjusting any of the analog or digital gain blocks will not require any modification of the transhybrid balance gain block, as the transhybrid gain is subtracted from the transmit path signal prior to any gain adjustment stages. if desired, the transhybrid balance can also be disabled using the appropriate register setting. 2.7.5. loopback testing four loopback test options are available in the proslic: ? the full analog loopback (alm2) tests almost all the circuitry of both the transmit and receive paths. the compressed 8-bit word tran smit data stream is fed back serially to the input of the receive path expander. (see figure 25.) the signal path starts with the analog signal at the input of the transmit
si3210/si3211 rev. 1.45 51 path and ends with an analog signal at the output of the receive path. ? an additional analog loopback (alm1) takes the digital stream at the output of the a/d converter and feeds it back to the d/a converter. (see figure 25.) the signal path starts with the analog signal at the input of the transmit path and ends with an analog signal at the output of the receive path. this loopback option allows testing of the analog signal processing circuitry of the si3210 to be carried out completely independently of any activity in the dsp. ? the full digital loopback tests almost all the circuitry of both the transmit and receive paths. the analog signal at the output of the receive path are fed back to the input of the transmit path by way of the hybrid filter path. (see figure 25.) the signal path starts with 8-bit pcm data input to the receive path and ends with 8-bit pcm data at the output of the transmit path. the user can bypass the companding process and interface directly to the 16-bit data. ? an additional digital loopback (dlm) takes the digital stream at the input of the d/a converter in the receive path and feeds it back to the transmit a/d digital filter. the signal path starts with 8-bit pcm data input to the receive path and ends with 8-bit pcm data at the output of the transmit path. this loopback option allows the testing of the digital signal processing circuitry of the si3210 to be carried out completely independently of any analog signal processing activity. the user can bypass the companding process and interface directly to the 16- bit data. 2.8. two-wire impedance matching the proslic provides on-chip, programmable, two-wire impedance settings to meet a wide variety of worldwide two-wire return loss requirements. the two-wire impedance is programmed by loading one of the eight available impedance values into the tiss[2:0] bits of the two-wire impedance synthesis control register (direct register 10). if direct register 10 is not user-defined, the default setting of 600 ? will be loaded into the tiss register. real and complex two-wire impedances are realized by internal feedback of a programmable amplifier (rac), a switched capacitor network (xac), and a transconductance amplifier (g m ). (see figure 25.) rac creates the real portion, and xac creates the imaginary portion of g m ?s input. g m then creates a current that models the desired impedance value to the subscriber loop. the differential ac current is fed to the subscriber loop via the itipp and iringp pins through an off-chip current buffer, i buf , which is implemented using transistors q1 and q2 (see figure 13 on page 24). g m is referenced to an off-chip resistor (r 15 ). the proslic also provides a means of compensating for degraded subscriber lo op conditions involving excessive line capacitance (l eakage). the clc[1:0] bits of direct register 10 incr ease the ac signal magnitude to compensate for the additional loss at the high end of the audio frequency range. the default setting of clc[2:0] assumes no line capacitance. silicon revisions c and high er support the option to remove the internal reference resistor used to synthesize ac impedances for 600 + 2.16 f and 900 + 2.16 f settings so that an external resistor reference may be used. this option is enabled by setting zsext = 1 (direct register 108, bit 4). 2.9. clock generation the proslic will generate the necessary internal clock frequencies from the pclk input. pclk must be synchronous to the 8 khz fsync clock and run at one of the following rates: 256 khz, 512 khz, 768 khz, 1.024 mhz, 1.536 mhz, 2.048 mhz, 4.096 mhz or 8.192 mhz. (note that 768 khz and 1.536 mhz are not valid rates for gci mode.) th e ratio of the pclk rate to the fsync rate is determined via a counter clocked by pclk. the three-bit ratio information is automatically transferred into an internal register, pll_mult, following a reset of the proslic. the pll_mult is used to control the internal pll, which multiplies pclk as needed to generate the 16.384 mhz rate needed to run the internal filters and other circuitry. the pll clock synthesizer se ttles very quickly following powerup. however, the settling time depends on the pclk frequency, and it can be approximated by the following equation: 2.10. interrupt logic the proslic is capable of generating interrupts for the following events: ? loop current/ring ground detected ? ring trip detected ? power alarm ? dtmf digit detected ? active timer 1 expired ? inactive timer 1 expired ? active timer 2 expired ? inactive timer 2 expired ? ringing active timer expired ? ringing inactive timer expired t settle 64 f pclk ---------------- - =
si3210/si3211 52 rev. 1.45 ? pulse metering active timer expired ? pulse metering inactive timer expired ? indirect register access complete the interface to the interrupt logic consists of six registers. three interrupt status registers contain one bit for each of the above interr upt functions. these bits will be set when an interrupt is pending for the associated resource. three interrupt enable registers also contain one bit for each interrupt fu nction. in the case of the interrupt enable registers, the bits are active high. refer to the appropriate functional description section for operational details of the interrupt functions. when a resource reaches an interrupt condition, it will signal an interrupt to the interrupt control block. the interrupt control block will then set the associated bit in the interrupt status register if the enable bit for that interrupt is set. the int pin is a nor of the bits of the interrupt status registers. therefore, if a bit in the interrupt status re gisters is asserted, irq will assert low. upon receiving the interrupt, the interrupt handler should read interrupt status registers to determine which resource is requesting service. to clear a pending interrupt, write the desired bit in the appropriate interrupt status register to 1. writing a 0 has no effect. this provides a mechanism fo r clearing individual bits when multiple interrupts oc cur simultaneously. while the interrupt status re gisters are non-zero, the int pin will remain asserted. 2.11. serial peripheral interface the control interface to the proslic is a 4-wire interface modeled after commonly-available micro-controller and serial peripheral devices. the interface consists of a clock (sclk), chip select (cs ), serial data input (sdi), and serial data output (sdo). data is transferred a byte at a time with each register access consisting of a pair of byte transfers. figures 26 and 27 illustrate read and write operation in the spi bus. the first byte of the pair is the command/address byte. the msb of this byte indicates a register read when 1 and a register write when 0. the remaining seven bits of the command/address byte indicate the address of the register to be accessed. the second byte of the pair is the data byte. because the falling edge of cs provides resynchronization of the spi state machine in the event of a framing error, it is recommended (but not required) that cs be taken high between byte transfers as shown in figures 26 and 27. during a read operation, the sdo becomes active and the 8-bit contents of the register are driven out msb first. the sdo will be high impedence on either the falling edge of sclk following the lsb, or the rising of cs as specified by the spim bit (direct register 0, bit 6). sdi is a ?don?t care? during the data portion of read operations. during write operations, data is driven into the proslic via the sdi pin msb first. the sdo pin will remain high impedance du ring write operations. data always transitions with the falling edge of the clock and is latched on the rising edge. the clock should return to a logic high when no transfer is in progress. indirect registers are accessed through direct registers 29 through 30. instructions on how to access them is described in ?3. control registers? beginning on page 59. there are a number of variations of usage on this four- wire interface: ? continuous clocking: during continuous clocking, the data transfers are controlled by the assertion of the cs pin. cs must assert before the falling edge of sclk on which the first bit of data is expected during a read cycle, and must remain low for the duration of the 8-?bit transfer (command/address or data). ? sdi/sdo wired operation: independent of the clocking options described, sdi and sdo can be treated as two separate lines or wired together if the master is capable of tristating its output during the data byte transfer of a read operation. ? daisy chain mode: this mode allows communication with banks of up to eight proslic devices using one chip select signal. when the spidc bit in the spi mode select register is set, data transfer mode changes to a 3-byte operation: a chip select byte, an address/control byte, and a data byte. using the circuit show n in figure 28, a single device may select from the bank of devices by setting the appropriate chip select bit to 1. each device uses the lsb of the chip select byte, shifts the data right by one bit, and passes the chip select byte using the sdithru pin to the next device in the chain. address/control and data bytes are unaltered.
si3210/si3211 rev. 1.45 53 figure 26. serial write 8-bit mode figure 27. serial read 8-bit mode sclk cs sdi sdo high impedance 0 a0 a1 a2 a3 a4 a5 a6 d7 d0 d1 d2 d3 d4 d5 d6 don't care sclk cs sdi sdo 1 a0 a1 a2 a3 a4 a5 a6 d7 d0 d1 d2 d3 d4 d5 d6 don't care high impedance don't care
si3210/si3211 54 rev. 1.45 figure 28. spi daisy chain mode cpu sdo cs sdi cs sdi sdithru sdo cs sdi sdithru sdo c7 c6 c5 c4 c3 c2 c1 c0 r/w a6 a5 a4 a3 a2 a1 a0 ? c7 c6 c5 c4 c3 c2 c1 ? ? c7 c6 c5 c4 c3 c2 chip select byte address byte data byte sclk sdi0 sdi1 sdi2 sdi3 r/w a6 a5 a4 a3 a2 a1 a0 r/w a6 a5 a4 a3 a2 a1 a0 r/w a6 a5 a4 a3 a2 a1 a0 ? ? ? c7 c6 c5 c4 c3 note: during chip select byte, sdithru = sdi delayed by one sclk. each device daisy-chained looks at the lsb of the chip select byte for its chip select. cs sdi sdithru sdo cs sdi sdithru sdo sdi0 sdi3 sdi2 sdi1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
si3210/si3211 rev. 1.45 55 2.12. pcm interface the proslic contains a flexible programmable interface for the transmission and reception of digital pcm samples. pcm data transfer is controlled via the pclk and fsync inputs as well as pcm mode select (direct register 1), pcm transmit start count (direct registers 2 and 3), and pcm receive start count (direct registers 4 and 5). the interface can be configured to support from 4 to 128 8-bit ti meslots in each frame. this corresponds to pclk frequencies of 256 khz to 8.192 mhz in power of 2 increments. (768 khz and 1.536 mhz are also available, but these frequencies are not valid for gci mode.) time slots for data transmission and reception are independently configured using the txs and rxs registers. by setting the correct starting point of the data, the proslic can be configured to support long fsync and short fsync variants as well as idl2 8-bit, 10-bit, b1 and b2 channel time slots. dtx data is high-impedance except for the duration of the 8- bit pcm transmit. dtx will return to high impedance either on the negative edge of pclk during the lsb or on the positive edge of pclk following the lsb. this is based on the setting of the tri bit of the pcm mode select register. tristating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention. in addition to 8-bit data modes, there is a 16-bit mode provided. this mode can be activated via the pcmt bit of the pcm mode select register. gci timing is also supported in which the duration of a data bit is two pclk cycles. this mode is also activated via the pcm mode select register. setting the txs or rxs register greater than the nu mber of pclk cycles in a sample period will stop data transmission because txs or rxs will never equal the pclk count. figures 29?32 illustrate the usage of t he pcm highway interface to adapt to common pcm standards. figure 29. example, timeslot 1, short fsync (txs/rxs = 1) 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx
si3210/si3211 56 rev. 1.45 figure 30. example, timeslot 1, long fsync (txs/rxs = 0) figure 31. example, idl2 long fsync, b2, 10-bit mode (txs/rxs = 10) figure 32. gci example, timeslot 1 (txs/rxs = 0) 2.13. companding the proslic supports both -255 law and a-law companding formats in addition to linear data. these 8- bit companding schemes follow a segmented curve formatted as sign bit, three chord bits, and four step bits. -255 law is more commonly used in north america and japan, while a-law is primarily used in europe. data format is selected via the pcmf register. tables 34 and 35 define the -law and a-law encoding formats. 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx 01 7 6 5 4 3 2 16 15 14 13 12 11 10 9 818 17 msb lsb hi-z hi-z pclk fsync pclk_cnt drx dtx
si3210/si3211 rev. 1.45 57 table 34. -law encode-decode characteristics 1,2 segment number #intervals x interval size value at segment endpoints digital code decode level 8 16 x 256 8159 . . . 4319 4063 10000000b 1000 1111b 8031 4191 7 16 x 128 . . . 2143 2015 100 11111b 2079 616 x 64 . . . 1055 991 1010 1111b 1023 516 x 32 . . . 511 479 10111111b 495 416 x 16 . . . 239 223 11001111b 231 316 x 8 . . . 103 95 11011111b 99 216 x 4 . . . 35 31 11101111b 33 1 15 x 2 __________________ 1 x 1 . . . 3 1 0 11111110b 11111111b 2 0 notes: 1. characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. digital code includes inversion of all magnitude bits.
si3210/si3211 58 rev. 1.45 table 35. a-law encode-decode characteristics 1,2 segment number #intervals x interval size value at segment endpoints digital code decode level 716 x 128 4096 3968 . . 2176 2048 10101010b 10100101b 4032 2112 616 x 64 . . . 1088 1024 10110101b 1056 516 x 32 . . . 544 512 10000101b 528 416 x 16 . . . 272 256 10010101b 264 3 16 x 8 . . . 136 128 11100101b 132 2 16 x 4 . . . 68 64 11110101b 66 1 32 x 2 . . . 2 0 11010101b 1 notes: 1. characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. digital code includes inversion of all even numbered bits.
si3210/si3211 rev. 1.45 59 3. control registers note: any register not listed here is re served and must not be written. table 36. direct register summary register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 setup 0 spi mode select spidc spim pni[1:0] rni[3:0] 1 pcm mode select pni2 pc me pcmf[1:0] pcmt gci tri 2 pcm transmit start count?low byte txs[7:0] 3 pcm transmit start count?high byte txs[9:8] 4 pcm receive start count?low byte rxs[7:0] 5 pcm receive start count?high byte rxs[9:8] 6 digital input/output control dout 1 dio2 1 dio1 1 pd2 1 pd1 1 audio 8 audio path loopback control alm2 dlm alm1 9 audio gain control rxhp t xhp txm rxm atx[1:0] arx[1:0] 10 two-wire impedance synthesis control clc[1:0] tise tiss[2:0] 11 hybrid control h ybp[2:0] hyba[2:0] powerdown 14 powerdown control 1 pmon dcof 2 mof biasof slicof 15 powerdown control 2 adcm adcon dacm dacon gmm gmon interrupts 18 interrupt status 1 pmip pmap rgip rgap o2ip o2ap o1ip o1ap 19 interrupt status 2 q6ap q5ap q4ap q3ap q2ap q1ap lcip rtip 20 interrupt status 3 cmcp indp dtmfp 21 interrupt enable 1 pmie pmae rgie rgae o2ie o2ae o1ie o1ae 22 interrupt enable 2 q6ae q5ae q4ae q3ae q2ae q1ae lcie rtie 23 interrupt enable 3 cmce inde dtmfe 24 decode status val dig[3:0] indirect register access notes: 1. si3211 only. 2. si3210 only.
si3210/si3211 60 rev. 1.45 28 indirect data access? low byte ida[7:0] 29 indirect data access? high byte ida[15:8] 30 indirect address iaa[7:0] 31 indirect address status ias oscillators 32 oscillator 1 control oss1 rel oz1 o1tae o1tie o1e o1so[1:0] 33 oscillator 2 control oss2 oz 2 o2tae o2tie o2e o2so[1:0] 34 ringing oscillator control rss rdac rtae rtie roe rvo tsws 35 pulse metering oscillator control pstat pmae pmie pmoe 36 oscillator 1 active timer?low byte oat1[7:0] 37 oscillator 1 active timer?high byte oat1[15:8] 38 oscillator 1 inactive timer?low byte oit1[7:0] 39 oscillator 1 inactive timer?high byte oit1[15:8] 40 oscillator 2 active timer?low byte oat2[7:0] 41 oscillator 2 active timer?high byte oat2[15:8] 42 oscillator 2 inactive timer?low byte oit2[7:0] 43 oscillator 2 inactive timer?high byte oit2[15:8] 44 pulse metering oscillator active timer? low byte pat[7:0] 45 pulse metering oscillator active timer? high byte pat[15:8] 46 pulse metering oscillator inactive timer?low byte pit[7:0] table 36. direct register summary (continued) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 1. si3211 only. 2. si3210 only.
si3210/si3211 rev. 1.45 61 47 pulse metering oscillator inactive timer?high byte pit[15:8] 48 ringing oscillator active timer?low byte rat[7:0] 49 ringing oscillator active timer?high byte rat[15:8] 50 ringing oscillator inac- tive timer?low byte rit[7:0] 51 ringing oscillator inac- tive timer?high byte rit[15:8] 52 fsk data fskdat slic 63 loop closure debounce interval for automatic ringing lcd[7:0] 64 linefeed control lfs[2:0] lf[2:0] 65 external bipolar transistor control sqh cby etbe etbo[1:0] etba[1:0] 66 battery feed control vov 2 fvbat 2 batsl 1 track 2 67 automatic/manual control mncm mndif spds abat aord aold aopn 68 loop closure/ring trip detect status dbiraw rtp lcr 69 loop closure debounce interval lcdi[6:0] 70 ring trip detect debounce interval rtdi[6:0] 71 loop current limit ilim[2:0] 72 on-hook line voltage vsgn voc[5:0] 73 common mode voltage vcm[5:0] 74 high battery voltage vbath[5:0] 75 low battery voltage vbatl[5:0] 76 power monitor pointer pwrmp[2:0] 77 line power output monitor pwrom[7:0] 78 loop voltage sense lvsp lvs[5:0] table 36. direct register summary (continued) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 1. si3211 only. 2. si3210 only.
si3210/si3211 62 rev. 1.45 79 loop current sense lcsp lcs[5:0] 80 tip voltage sense vtip[7:0] 81 ring voltage sense vring[7:0] 82 battery voltage sense 1 vbats1[7:0] 83 battery voltage sense 2 vbats2[7:0] 84 transistor 1 current sense iq1[7:0] 85 transistor 2 current sense iq2[7:0] 86 transistor 3 current sense iq3[7:0] 87 transistor 4 current sense iq4[7:0] 88 transistor 5 current sense iq5[7:0] 89 transistor 6 current sense iq6[7:0] 92 dc-dc converter pwm period dcn[7:0] 2 93 dc-dc converter switching delay dccal 2 dcpol 2 dctof[4:0] 2 94 dc-dc converter pwm pulse width dcpw[7:0] 2 95 reserved 96 calibration control/ status register 1 cal calsp calr calt cald calc calil 97 calibration control/ status register 2 calm1 calm2 caldac caladc calcm 98 ring gain mismatch calibration result calgmr[4:0] 99 tip gain mismatch calibration result calgmt[4:0] 100 differential loop current gain calibration result calgd[4:0] 101 common mode loop current gain calibration result calgc[4:0] table 36. direct register summary (continued) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 1. si3211 only. 2. si3210 only.
si3210/si3211 rev. 1.45 63 102 current limit calibration result calgil[3:0] 103 monitor adc offset calibration result calmg1[3:0] calmg2[3:0] 104 analog dac/adc offset dacp dacn adcp adcn 105 dac offset calibration result dacof[7:0] 106 common mode balance calibration result cmbal[5:0] 107 dc peak current calibration result cmdcpk[3:0] 108 enhancement enable ilimen fsken dcsu 2 zsext swdb lcve dcfil 2 hysten table 36. direct register summary (continued) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 1. si3211 only. 2. si3210 only.
si3210/si3211 64 rev. 1.45 reset settings = 00xx_xxxx register 0. spi mode select bitd7d6d5d4d3d2d1d0 name spidc spim pni[1:0] rni[3:0] type r/w r/w r r bit name function 7 spidc spi daisy chain mode enable. 0 = disable spi daisy chain mode. 1 = enable spi daisy chain mode. 6spim spi mode. 0 = causes sdo to tri-state on rising edge of sclk of lsb. 1 = normal operation; sdo tri-states on rising edge of cs . 5:4 pni[1:0] part number identification. 00 = si3210 01 = si3211 10 = unused 11 = si3210m 3:0 rni[3:0] revision number identification. 0001 = revision a, 0010 = revision b, 0011 = revision c, etc.
si3210/si3211 rev. 1.45 65 reset settings = 0000_1000 register 1. pcm mode select bitd7d6d5d4d3d2d1d0 name pni2 pcme pcmf[1:0] pcmt gci tri type r/w r/w r/w r/w r/w bit name function 7pni2 part number identification 2. 0 = si3210/11 family. 1 = si3215/16 family. 6 reserved read returns zero. 5pcme pcm enable. 0 = disable pcm transfers. 1 = enable pcm transfers. 4:3 pcmf[1:0] pcm format. 00 = a-law 01 = -law 10 = reserved 11 = linear 2pcmt pcm transfer size. 0 = 8-bit transfer. 1 = 16-bit transfer. 1gci gci clock format. 0 = 1 pclk per data bit. 1 = 2 pclks per data bit. 0tri tri-state bit 0. 0 = tri-state bit 0 on positive edge of pclk. 1 = tri-state bit 0 on negative edge of pclk.
si3210/si3211 66 rev. 1.45 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = 0000_0000 register 2. pcm transmit start count?low byte bitd7d6d5d4d3d2d1d0 name txs[7:0] type r/w bit name function 7:0 txs[7:0] pcm transmit start count. pcm transmit start count equals the number of pclks following fsync before data trans- mission begins. see figure 29 on page 55. register 3. pcm transmit start count?high byte bitd7d6d5d4d3d2d1d0 name txs[9:8] type r/w bit name function 7:2 reserved read returns zero. 1:0 txs[9:8] pcm transmit start count. pcm transmit start count equals the number of pclks following fsync before data transmission begins. see figure 29 on page 55. register 4. pcm receive start count?low byte bitd7d6d5d4d3d2d1d0 name rxs[7:0] type r/w bit name function 7:0 rxs[7:0] pcm receive start count. pcm receive start count equals the number of pclks following fsync before data reception begins. see figure 29 on page 55.
si3210/si3211 rev. 1.45 67 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = 0000_0000 register 5. pcm receive start count?high byte bitd7d6d5d4d3d2d1d0 name rxs[9:8] type r/w bit name function 7:2 reserved read returns zero. 1:0 rxs[9:8] pcm receive start count. pcm receive start count equals the number of pclks following fsync before data reception begins. see figure 29 on page 55. register 6. digital input/output control si3210 bitd7d6d5d4d3d2d1d0 name type si3211 bitd7d6d5d4d3d2d1d0 name dout dio2 dio1 pd2 pd1 type r/wr/wr/wr/wr/w
si3210/si3211 68 rev. 1.45 bit name function 7:5 reserved read returns zero. 4dout dout pin output data (si3211 only). 0 = dout pin driven low. 1 = dout pin driven high. si3210 = reserved. 3dio2 dio2 pin input/output direction (si3211 only). 0 = dio2 pin is an input. 1 = dio2 pin is an output and dr iven to value of the pd2 bit. si3210 = reserved. 2dio1 dio1 pin input/output direction (si3211 only). 0 = dio1 pin is an input. 1 = dio1 pin is an output and dr iven to value of the pd1 bit. si3210 = reserved. 1pd2 dio2 pin data (si3211 only). when dio2 = 1: 0 = dio2 pin driven low. 1 = dio2 pin driven high. si3210 = reserved. when dio2 = 0, pd2 value equals the logic input of dio2 pin. 0pd1 dio1 pin data (si3211 only). when dio1 = 1: 0 = dio1 pin driven low. 1 = dio1 pin driven high. si3210 = reserved. when dio1 = 0, pd1 value equals the logic input of dio1 pin.
si3210/si3211 rev. 1.45 69 reset settings = 0000_0010 register 8. audio path loopback control bitd7d6d5d4d3d2d1d0 name alm2 dlm alm1 type r/w r/w r/w bit name function 7:3 reserved read returns zero. 2alm2 analog loopback mode 2. (see figure 25 on page 49.) 0 = full analog loopback mode disabled. 1 = full analog loopback mode enabled. 1dlm digital loopback mode. (see figure 25 on page 49.) 0 = digital loopback disabled. 1 = digital loopback enabled. 0alm1 analog loopback mode 1. (see figure 25 on page 49.) 0 = analog loopback disabled. 1 = analog loopback enabled.
si3210/si3211 70 rev. 1.45 reset settings = 0000_0000 register 9. audio gain control bitd7d6d5d4d3d2d1d0 name rxhp txhp txm rxm atx[1:0] arx[1:0] type r/wr/wr/wr/w r/w r/w bit name function 7rxhp receive path high pass filter disable. 0 = hpf enabled in receive path, rhdf. 1 = hpf bypassed in receive path, rhdf. 6txhp transmit path high pass filter disable. 0 = hpf enabled in transmit path, thpf. 1 = hpf bypassed in transmit path, thpf. 5txm transmit path mute. refer to position of digital mute in figure 25 on page 49. 0 = transmit signal passed. 1 = transmit signal muted. 4rxm receive path mute. refer to position of digital mute in figure 25 on page 49. 0 = receive signal passed. 1 = receive signal muted. 3:2 atx[1:0] analog transmit path gain. 00 = 0 db 01 = ?3.5 db 10 = 3.5 db 11 = atx gain = 0 db; analog transmit path muted. 1:0 arx[1:0] analog receive path gain. 00 = 0 db 01 = ?3.5 db 10 = 3.5 db 11 = analog receive path muted.
si3210/si3211 rev. 1.45 71 reset settings = 0000_1000 register 10. two-wire impedance synthesis control bitd7d6d5d4d3d2d1d0 name clc[1:0] tise tiss[2:0] type r/w r/w r/w bit name function 7:6 reserved read returns zero. 5:4 clc[1:0] line capacitance compensation. 00 = off 01 = 4.7 nf 10 = 10 nf 11 = reserved 3tise two-wire impedance synthesis enable. 0 = two-wire impedance synthesis disabled. 1 = two-wire impedance synthesis enabled. 2:0 tiss[2:0] two-wire impedance synthesis selection. 000 = 600 ? 001 = 900 ? 010 = 600 ? + 2.16 f 011 = 900 ? + 2.16 f 100 = ctr21 (270 ? + 750 ? || 150 nf) 101 = australia/new zealand #1 (220 ? + 820 ? || 120 nf) 110 = slovakia/slovenia/south africa (220 ? + 820 ? || 115 nf) 111 = new zealand #2 (370 ? + 620 ? || 310 nf)
si3210/si3211 72 rev. 1.45 reset settings = 0011_0011 register 11. hybrid control bitd7d6d5d4d3d2d1d0 name hybp[2:0] hyba[2:0] type r/w r/w bit name function 7 reserved read returns zero. 6:4 hybp[2:0] pulse metering hybr id adjustment. 000 = 4.08 db 001 = 2.5 db 010 = 1.16 db 011=0db 100 = ?1.02 db 101 = ?1.94 db 110 = ?2.77 db 111 = off 3 reserved read returns zero. 2:0 hyba[2:0] audio hybrid adjustment. 000 = 4.08 db 001 = 2.5 db 010 = 1.16 db 011=0db 100 = ?1.02 db 101 = ?1.94 db 110 = ?2.77 db 111 = off
si3210/si3211 rev. 1.45 73 reset settings = 0001_0000 reset settings = 0001_0000 register 14. powerdown control 1 si3210 bitd7d6d5d4d3d2d1d0 name pmon dcof mof biasof slicof type r/w r/w r/w r/w r/w si3211 bitd7d6d5d4d3d2d1d0 name pmon mof biasof slicof type r/w r/w r/w r/w bit name function 7:6 reserved read returns zero. 5pmon pulse metering dac power-on control. 0 = automatic power control. 1 = override automatic control and forc e pulse metering dac circuitry on. 4 dcof dc-dc converter power-off control (si3210 only). 0 = automatic power control. 1 = override automatic control and force dc-dc circuitry off. si3211 = read returns 1; it cannot be written. 3mof monitor adc power-off control. 0 = automatic power control. 1 = override automatic control and force monitor adc circuitry off. 2 reserved read returns zero. 1 biasof dc bias power-off control. 0 = automatic power control. 1 = override automatic control an d force dc bias circuitry off. 0slicof slic power-off control. 0 = automatic power control. 1 = override automatic control and force slic circuitry off.
si3210/si3211 74 rev. 1.45 reset settings = 0000_0000 register 15. powerdown control 2 bitd7d6d5d4d3d2d1d0 name adcm adcon dacm dacon gmm gmon type r/w r/w r/w r/w r/w r/w bit name function 7:6 reserved read returns zero. 5 adcm analog to digital converter manual/automatic power control. 0 = automatic power control. 1 = manual power control; adcon controls on/off state. 4adcon analog to digital converter on/off power control. when adcm = 1: 0 = analog to digital converter powered off. 1 = analog to digital converter powered on. adcon has no effect when adcm = 0. 3dacm digital to analog converter manual/automatic power control. 0 = automatic power control. 1 = manual power control; dacon controls on/off state. 2dacon digital to analog converter on/off power control. when dacm = 1: 0 = digital to analog converter powered off. 1 = digital to analog converter powered on. dacon has no effect when dacm = 0. 1gmm transconductance amplifier manual/automatic power control. 0 = automatic power control. 1 = manual power control; gmon controls on/off state. 0gmon transconductance amplifie r on/off power control. when gmm = 1: 0 = analog to digital converter powered off. 1 = analog to digital converter powered on. gmon has no effect when gmm = 0.
si3210/si3211 rev. 1.45 75 reset settings = 0000_0000 register 18. interrupt status 1 bitd7d6d5d4d3d2d1d0 name pmip pmap rgip rgap o2ip o2ap o1ip o1ap type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7pmip pulse metering inactive timer interrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 6pmap pulse metering active timer interrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 5rgip ringing inactive timer interrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 4rgap ringing active timer interrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 3o2ip oscillator 2 inactive timer interrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 2o2ap oscillator 2 active ti mer interrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 1o1ip oscillator 1 inactive timer interrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 0o1ap oscillator 1 active ti mer interrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending.
si3210/si3211 76 rev. 1.45 reset settings = 0000_0000 register 19. interrupt status 2 bitd7d6d5d4d3d2d1d0 name q6ap q5ap q4ap q3ap q2ap q1ap lcip rtip type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7q6ap power alarm q6 in terrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 6q5ap power alarm q5 in terrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 5q4ap power alarm q4 in terrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 4q3ap power alarm q3 in terrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 3q2ap power alarm q2 in terrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 2q1ap power alarm q1 in terrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 1lcip loop closure transition interrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 0rtip ring trip interrupt pending. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending.
si3210/si3211 rev. 1.45 77 reset settings = 0000_0000 register 20. interrupt status 3 bitd7d6d5d4d3d2d1d0 name cmcp indp dtmfp type r/w r/w r/w bit name function 7:3 reserved read returns zero. 2cmcp common mode calibration error interrupt. this bit is set when off-hook/on-hook status changes during the common mode balance calibration. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 1indp indirect register acce ss serviced interrupt. this bit is set once a pending indirect register service request has been completed. writ- ing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending. 0 dtmfp dtmf tone detected interrupt. writing 1 to this bit clears a pending interrupt. 0 = no interrupt pending. 1 = interrupt pending.
si3210/si3211 78 rev. 1.45 reset settings = 0000_0000 register 21. interrupt enable 1 bitd7d6d5d4d3d2d1d0 name pmie pmae rgie rgae o2ie o2ae o1ie o1ae type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7pmie pulse metering inactive timer interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 6pmae pulse metering active ti mer interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 5rgie ringing inactive timer interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 4rgae ringing active timer interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 3o2ie oscillator 2 inactive timer interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 2o2ae oscillator 2 active ti mer interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 1o1ie oscillator 1 inactive timer interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 0o1ae oscillator 1 active ti mer interrupt enable. 0 = interrupt masked. 1 = interrupt enabled.
si3210/si3211 rev. 1.45 79 reset settings = 0000_0000 register 22. interrupt enable 2 bitd7d6d5d4d3d2d1d0 name q6ae q5ae q4ae q3ae q2ae q1ae lcie rtie type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7q6ae power alarm q6 interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 6q5ae power alarm q5 interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 5q4ae power alarm q4 interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 4q3ae power alarm q3 interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 3q2ae power alarm q2 interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 2q1ae power alarm q1 interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 1lcie loop closure transition interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 0rtie ring trip interrupt enable. 0 = interrupt masked. 1 = interrupt enabled.
si3210/si3211 80 rev. 1.45 reset settings = 0000_0000 register 23. interrupt enable 3 bitd7d6d5d4d3d2d1d0 name cmce inde dtmfe type r/w r/w r/w bit name function 7:3 reserved read returns zero. 2cmce common mode calibration error interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 1inde indirect register access serviced interrupt enable. 0 = interrupt masked. 1 = interrupt enabled. 0 dtmfe dtmf tone detected interrupt enable. 0 = interrupt masked. 1 = interrupt enabled.
si3210/si3211 rev. 1.45 81 reset settings = 0000_0000 register 24. dtmf decode status bitd7d6d5d4d3d2d1d0 name val dig[3:0] type rr bit name function 7:5 reserved read returns zero. 4val dtmf valid digit decoded. 0 = not currently detecting digit. 1 = currently detecting digit. 3:0 dig[3:0] dtmf digit. 0001 = ?1? 0010 = ?2? 0011 = ?3? 0100 = ?4? 0101 = ?5? 0110 = ?6? 0111 = ?7? 1000 = ?8? 1001 = ?9? 1010 = ?0? 1011 = ?*? 1100 = ?#? 1101 = ?a? 1110 = ?b? 1111 = ?c? 0000 = ?d?
si3210/si3211 82 rev. 1.45 reset settings = 0000_0000 reset settings = 0000_0000 register 28. indirect data access?low byte bitd7d6d5d4d3d2d1d0 name ida[7:0] type r/w bit name function 7:0 ida[7:0] indirect data access?low byte. a write to ida followed by a write to iaa will pl ace the contents of ida into an indirect register at the location referenced by iaa at the next indirect register update (16 khz update rate?a write op eration). writing iaa only will load ida with the value stored at iaa at the next indirect memory update (a read operation). register 29. indirect data access?high byte bitd7d6d5d4d3d2d1d0 name ida[15:8] type r/w bit name function 7:0 ida[15:8] indirect data access?high byte. a write to ida followed by a write to iaa will pl ace the contents of ida into an indirect register at the location referenced by iaa at the next indirect register update (16 khz update rate?a write op eration). writing iaa only will load ida with the value stored at iaa at the next indirect memory update (a read operation).
si3210/si3211 rev. 1.45 83 reset settings = xxxx_xxxx reset settings = 0000_0000 register 30. indirect address bitd7d6d5d4d3d2d1d0 name iaa[7:0] type r/w bit name function 7:0 iaa[7:0] indirect address access. a write to ida followed by a write to iaa will pl ace the contents of ida into an indirect register at the location referenced by iaa at the next indirect register update (16 khz update rate?a write op eration). writing iaa only will load ida with the value stored at iaa at the next indirect memory update (a read operation). register 31. indirect address status bitd7d6d5d4d3d2d1d0 name ias type r bit name function 7:1 reserved read returns zero. 0ias indirect access status. 0 = no indirect memory access pending. 1 = indirect memory access pending.
si3210/si3211 84 rev. 1.45 reset settings = 0000_0000 register 32. oscillator 1 control bitd7d6d5d4d3d2d1d0 name oss1 rel oz1 o1tae o1tie o1e o1so[1:0] type r r/w r/w r/w r/w r/w r/w bit name function 7 oss1 oscillator 1 signal status. 0 = output signal inactive. 1 = output signal active. 6rel oscillator 1 automatic register reload. this bit should be set for fsk signaling. 0 = oscillator 1 will stop signaling after inactive timer expires. 1 = oscillator 1 will continue to read re gister parameters and output signals. 5oz1 oscillator 1 zero cross enable. 0 = signal terminates after active timer expires. 1 = signal terminates at zero crossing after active timer expires. 4o1tae oscillator 1 active timer enable. 0=disable timer. 1 = enable timer. 3o1tie oscillator 1 inactive timer enable. 0=disable timer. 1 = enable timer. 2o1e oscillator 1 enable. 0 = disable oscillator. 1 = enable oscillator. 1:0 o1so[1:0] oscillator 1 signal output routing. 00 = unassigned path (output not connected). 01 = assign to transmit path. 10 = assign to receive path. 11 = assign to both paths.
si3210/si3211 rev. 1.45 85 reset settings = 0000_0000 register 33. oscillator 2 control bitd7d6d5d4d3d2d1d0 name oss2 oz2 o2tae o2tie o2e o2so[1:0] type r r/w r/w r/w r/w r/w bit name function 7 oss2 oscillator 2 signal status. 0 = output signal inactive. 1 = output signal active. 6 reserved read returns zero. 5oz2 oscillator 2 zero cross enable. 0 = signal terminates after active timer expires. 1 = signal terminates at zero crossing. 4o2tae oscillator 2 active timer enable. 0=disable timer. 1 = enable timer. 3o2tie oscillator 2 inactive timer enable. 0=disable timer. 1 = enable timer. 2o2e oscillator 2 enable. 0 = disable oscillator. 1 = enable oscillator. 1:0 o2so[1:0] oscillator 2 signal output routing. 00 = unassigned path (output not connected) 01 = assign to transmit path. 10 = assign to receive path. 11 = assign to both paths.
si3210/si3211 86 rev. 1.45 reset settings = 0000_0000 register 34. ringing oscillator control bitd7d6d5d4d3d2d1d0 name rss rdac rtae rtie roe rvo tsws type rrr/wr/wrr/wr/w bit name function 7rss ringing signal status. 0 = ringing oscillator out put signal inactive. 1 = ringing oscillator output signal active. 6 reserved read returns zero. 5 rdac ringing signal dac/linefeed cross indicator. for ringing signal start and stop, output to tip and ring is suspended to ensure conti- nuity with dc linefeed voltages. rdac indicates that ringing si gnal is actually present at tip and ring. 0 = ringing signal not present at tip and ring. 1 = ringing signal present at tip and ring. 4rtae ringing active timer enable. 0=disable timer. 1 = enable timer. 3rtie ringing inactive timer enable. 0=disable timer. 1 = enable timer. 2roe ringing oscillator enable. 0 = ringing oscillator disabled. 1 = ringing oscillator enabled. 1rvo ringing voltage offset. 0 = no dc offset added to ringing signal. 1 = dc offset added to ringing signal. 0tsws trapezoid/sinusoid waveshape select. 0 = sinusoid 1 = trapezoid
si3210/si3211 rev. 1.45 87 reset settings = 0000_0000 reset settings = 0000_0000 register 35. pulse metering oscillator control bitd7d6d5d4d3d2d1d0 name pstat pmae pmie pmoe type r r/w r/w r/w bit name function 7 pstat pulse metering signal status. 0 = output signal inactive. 1 = output signal active. 6:5 reserved read returns zero. 4pmae pulse metering active timer enable. 0=disable timer. 1 = enable timer. 3pmie pulse metering inacti ve timer enable. 0=disable timer. 1 = enable timer. 2pmoe pulse metering oscillator enable. 0 = disable oscillator. 1 = enable oscillator. 1:0 reserved read returns zero. register 36. oscillator 1 active timer?low byte bitd7d6d5d4d3d2d1d0 name oat1[7:0] type r/w bit name function 7:0 oat1[7:0] oscillator 1 active timer. lsb = 125 s
si3210/si3211 88 rev. 1.45 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = 0000_0000 register 37. oscillator 1 active timer?high byte bitd7d6d5d4d3d2d1d0 name oat1[15:8] type r/w bit name function 7:0 oat1[15:8] oscillator 1 active timer. register 38. oscillator 1 inactive timer?low byte bitd7d6d5d4d3d2d1d0 name oit1[7:0] type r/w bit name function 7:0 oit1[7:0] oscillator 1 inactive timer. lsb = 125 s register 39. oscillator 1 inactive timer?high byte bitd7d6d5d4d3d2d1d0 name oit1[15:8] type r/w bit name function 7:0 oit1[15:8] oscillator 1 inactive timer.
si3210/si3211 rev. 1.45 89 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = 0000_0000 register 40. oscillator 2 active timer?low byte bitd7d6d5d4d3d2d1d0 name oat2[7:0] type r/w bit name function 7:0 oat2[7:0] oscillator 2 active timer. lsb = 125 s register 41. oscillator 2 active timer?high byte bitd7d6d5d4d3d2d1d0 name oat2[15:8] type r/w bit name function 7:0 oat2[15:8] oscillator 2 active timer. register 42. oscillator 2 inactive timer?low byte bitd7d6d5d4d3d2d1d0 name oit2[7:0] type r/w bit name function 7:0 oit2[7:0] oscillator 2 inactive timer. lsb = 125 s
si3210/si3211 90 rev. 1.45 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = 0000_0000 register 43. oscillator 2 inactive timer?high byte bitd7d6d5d4d3d2d1d0 name oit2[15:8] type r/w bit name function 7:0 oit2[15:8] oscillator 2 inactive timer. register 44. pulse metering oscillator active timer?low byte bitd7d6d5d4d3d2d1d0 name pat[7:0] type r/w bit name function 7:0 pat[7:0] pulse metering active timer. lsb = 125 s register 45. pulse metering oscillator active timer?high byte bitd7d6d5d4d3d2d1d0 name pat[15:8] type r/w bit name function 7:0 pat[15:8] pulse metering active timer.
si3210/si3211 rev. 1.45 91 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = 0000_0000 register 46. pulse metering oscillator inactive timer?low byte bitd7d6d5d4d3d2d1d0 name pit[7:0] type r/w bit name function 7:0 pit[7:0] pulse metering inactive timer. lsb = 125 s register 47. pulse metering oscillator inactive timer?high byte bitd7d6d5d4d3d2d1d0 name pit[15:8] type r/w bit name function 7:0 pit[15:8] pulse metering inactive timer. register 48. ringing oscillator active timer?low byte bitd7d6d5d4d3d2d1d0 name rat[7:0] type r/w bit name function 7:0 rat[7:0] ringing active timer. lsb = 125 s
si3210/si3211 92 rev. 1.45 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = 0000_0000 register 49. ringing oscillator active timer?high byte bitd7d6d5d4d3d2d1d0 name rat[15:8] type r/w bit name function 7:0 rat[15:8] ringing active timer. register 50. ringing oscillator inactive timer?low byte bitd7d6d5d4d3d2d1d0 name rit[7:0] type r/w bit name function 7:0 rit[7:0] ringing inactive timer. lsb = 125 s register 51. ringing oscillator inactive timer?high byte bitd7d6d5d4d3d2d1d0 name rit[15:8] type r/w bit name function 7:0 rit[15:8] ringing inactive timer.
si3210/si3211 rev. 1.45 93 reset settings = 0000_0000 reset settings = 0011_0010 (revision c); 0101_0100 (subsequent revisions) register 52. fsk data bitd7d6d5d4d3d2d1d0 name fskdat type r/w bit name function 7:1 reserved read returns zero. 0 fskdat fsk data. when fsken = 1 (direct register 108, bit 6) an d rel = 1 (direct register 32, bit 6), this bit serves as the buffered input for fsk generation bit stream data. register 63. loop closure debounce interval bitd7d6d5d4d3d2d1d0 name lcd[7:0] type bit name function 7:0 lcd[7:0] loop closure debounce interval for automatic ringing. this register sets the loop closure debounce interval for the ringing silent period when using automatic ringing cadences. the value may be set between 0 ms (0x00) and 159 ms (0x7f) in 1.25 ms steps.
si3210/si3211 94 rev. 1.45 reset settings = 0000_0000 register 64. linefeed control bitd7d6d5d4d3d2d1d0 name lfs[2:0] lf[2:0] type rr/w bit name function 7 reserved read returns zero. 6:4 lfs[2:0] linefeed shadow. this register reflects the actual real-time linefeed state. automatic operations may cause actual linefeed state to deviate from the st ate defined by linefeed register (e.g., when linefeed equals ringing state, lfs will equal on-hook transmission st ate during ringing silent period and ringing state during ring burst). 000 = open 001 = forward active 010 = forward on-hook transmission 011 = tip open 100 = ringing 101 = reverse active 110 = reverse on-hook transmission 111 = ring open 3 reserved read returns zero. 2:0 lf[2:0] linefeed. writing to this register sets the linefeed state. 000 = open 001 = forward active 010 = forward on-hook transmission 011 = tip open 100 = ringing 101 = reverse active 110 = reverse on-hook transmission 111 = ring open
si3210/si3211 rev. 1.45 95 reset settings = 0110_0001 register 65. external bipolar transistor control bitd7d6d5d4d3d2d1d0 name sqh cby etbe etbo[1:0] etba[1:0] type r/w r/w r/w r/w r/w bit name function 7 reserved read returns zero. 6sqh audio squelch. 0 = no squelch. 1 = stipac and sringac pins squelched. 5cby capacitor bypass. 0 = capacitors cp (c1) and cm (c2) in circuit. 1 = capacitors cp (c1) and cm (c2) bypassed. 4etbe external transistor bias enable. 0 = bias disabled. 1 = bias enabled. 3:2 etbo[1:0] external transistor bias levels?on-hook transmission state. dc bias current which flows through external bjts in the on-hook transmission state. increasing this value increases the compliance of the ac longitudinal balance circuit. 00 = 4 ma 01 = 8 ma 10 = 12 ma 11 = reserved 1:0 etba[1:0] external transistor bias levels?active off-hook state. dc bias current which flows through external bjts in the active off-hook state. increasing this value increases the compliance of the ac longitudinal balance circuit. 00 = 4 ma 01 = 8 ma 10 = 12 ma 11 = reserved
si3210/si3211 96 rev. 1.45 reset settings = 0000_0011 reset settings = 0000_0110 register 66. battery feed control si3210 bitd7d6d5d4d3d2d1d0 name vov fvbat track type r/w r/w r/w si3211 bitd7d6d5d4d3d2d1d0 name batsl type r/w bit name function 7:5 reserved read returns zero. 4vov overhead voltage range increase. (si3210 only; see figure 19 on page 38.) this bit selects the programmable range for v ov , which is defined in indirect register 41. 0=v ov = 0 v to 9 v 1=v ov = 0 v to 13.5 v si3211 = reserved. 3fvbat v bat manual setting (si3210 only). 0 = normal operation 1=v bat tracks v bath register. si3211 = read returns 0; it cannot be written. 2 reserved si3210 = read returns zero. si3211 = read returns one. 1batsl battery feed select (si3211 only). this bit selects between high and low battery supplies. 0 = low battery selected (dcsw pin low). 1 = high battery selected (dcsw pin high). si3210 = read returns zero. 0track dc-dc converter tracking mode (si3210 only). 0=|v bat | will not decrease below vbatl. 1=v bat tracks v ring . si3211 = reserved.
si3210/si3211 rev. 1.45 97 reset settings = 0001_1111 register 67. automatic/manual control bitd7d6d5d4d3d2d1d0 name mncm mndif spds abat aord aold aopn type r/w r/w r/w r/w r/w r/w r/w bit name function 7 reserved read returns zero. 6 mncm common mode manual/a utomatic select. 0 = automatic control. 1 = manual control, in which tip (forward) or ring (reverse) forces voltage to follow vcm value. 5 mndif differential mode manu al/automatic select. 0 = automatic control. 1 = manual control (forces differential voltage to follow voc value). 4 spds speed-up mode enable. 0 = speed-up disabled. 1 = automatic speed-up. 3abat battery feed automatic/manual select (si3211 only). 0 = automatic mode disabled. 1 = automatic mode enabled (automatic switching to low battery in off-hook state). 2aord automatic/manual ring trip detect. 0 = manual mode. 1 = enter off-hook active state auto matically upon ring trip detect. 1aold automatic/manual loop closure detect. 0 = manual mode. 1 = enter off-hook active state automatically upon loop closure detect. 0aopn power alarm automati c/manual detect. 0 = manual mode. 1 = enter open state automatically upon power alarm.
si3210/si3211 98 rev. 1.45 reset settings = 0000_0000 reset settings = 0000_1010 register 68. loop closure/ring trip detect status bitd7d6d5d4d3d2d1d0 name dbiraw rtp lcr type rrr bit name function 7:3 reserved read returns zero. 2dbiraw ring trip/loop closure unfiltered output. state of this bit reflects the real-time output of ring trip and loop closure detect circuits before debouncing. 0 = ring trip/loop closure threshold exceeded. 1 = ring trip/loop closure threshold not exceeded. 1rtp ring trip detect indica tor (filtered output). 0 = ring trip detect has not occurred. 1 = ring trip de tect occurred. 0lcr loop closure detect indicator (filtered output). 0 = loop closure detect has not occurred. 1 = loop closure detect has occurred. register 69. loop closure debounce interval bitd7d6d5d4d3d2d1d0 name lcdi[6:0] type r/w bit name function 7 reserved read returns zero. 6:0 lcdi[6:0] loop closure debounce interval. the value written to this register defines the minimum steady state debounce time. value may be set between 0 ms (0x00) to 159 ms (0x7f) in 1.25 ms steps. default value = 12.5 ms.
si3210/si3211 rev. 1.45 99 reset settings = 0000_1010 reset settings = 0000_0000 register 70. ring trip detect debounce interval bitd7d6d5d4d3d2d1d0 name rtdi[6:0] type r/w bit name function 7 reserved read returns zero. 6:0 rtdi[6:0] ring trip detect debounce interval. the value written to this register defines the minimum steady state debounce time. the value may be set between 0 ms (0x00) to 159 ms (0x7f) in 1.25 ms steps. default value = 12.5 ms. register 71. loop current limit bitd7d6d5d4d3d2d1d0 name ilim[2:0] type r/w bit name function 7:3 reserved read returns zero. 2:0 ilim[2:0] loop current limit. the value written to this register sets the constant loop current. the value may be set between 20 ma (0x00) and 41 ma (0x07) in 3 ma steps.
si3210/si3211 100 rev. 1.45 reset settings = 0010_0000 reset settings = 0000_0010 register 72. on-hook line voltage bitd7d6d5d4d3d2d1d0 name vsgn voc[5:0] type r/w r/w bit name function 7 reserved read returns zero. 6 vsgn on-hook line voltage. the value written to this bit sets the on-hook line voltage polarity (v tip ?v ring ). 0=v tip ?v ring is positive 1=v tip ?v ring is negative 5:0 voc[5:0] on-hook line voltage. the value written to this register sets the on-hook line voltage (v tip ?v ring ). value may be set between 0 v (0x00) and 94.5 v (0x3f) in 1.5 v steps. default value = 48 v. register 73. common mode voltage bitd7d6d5d4d3d2d1d0 name vcm[5:0] type r/w bit name function 7:6 reserved read returns zero. 5:0 vcm[5:0] common mode voltage. the value written to this register sets v tip for forward active and forward on-hook trans- mission states and v ring for reverse active and reverse on-hook transmission states. the value may be set between 0 v (0x00) and ?94.5 v (0x3f) in 1.5 v steps. default value = ?3 v.
si3210/si3211 rev. 1.45 101 reset settings = 0011_0010 reset settings = 0001_0000 register 74. high battery voltage bitd7d6d5d4d3d2d1d0 name vbath[5:0] type r/w bit name function 7:6 reserved read returns zero. 5:0 vbath[5:0] high battery voltage. the value written to this register sets high battery voltage. v bath must be greater than or equal to vbatl. the value may be set between 0 v (0x00) and ?94.5 v (0x3f) in 1.5 v steps. default value = ?75 v. for si3211, v batl must be set equal to the voltage supplied at the v batl node shown in the si3211 typical application circuit drawings, figure 12 on page 22 and figure 14 on page 26. register 75. low battery voltage bitd7d6d5d4d3d2d1d0 name vbatl[5:0] type r/w bit name function 7:6 reserved read returns zero. 5:0 vbatl[5:0] low battery voltage. the value written to this regist er sets low battery voltage. v bath must be greater than or equal to v batl . the value may be set between 0 v (0x00) and ?94.5 v (0x3f) in 1.5 v steps. default value = ?24 v. for si3211, v batl must be set equal to the voltage supplied at the v batl node shown in the si3211 typical application circuit drawings, figure 12 on page 22 and figure 14 on page 26.
si3210/si3211 102 rev. 1.45 reset settings = 0000_0000 reset settings = 0000_0000 register 76. power monitor pointer bitd7d6d5d4d3d2d1d0 name pwrmp[2:0] type r/w bit name function 7:3 reserved read returns zero. 2:0 pwrmp[2:0] power monitor pointer. selects the external transistor from which to read power output. the power of the selected transistor is read in the pwrom register. 000 = q1 001 = q2 010 = q3 011 = q4 100 = q5 101 = q6 110 = undefined 111 = undefined register 77. line power output monitor bitd7d6d5d4d3d2d1d0 name pwrom[7:0] type r bit name function 7:0 pwrom[7:0] line power output monitor. this register reports the real-time power ou tput of the transistor selected using pwrmp. the range is 0 w (0x00) to 7.8 w (0xff) in 30.4 mw steps for q1, q2, q5, and q6. the range is 0 w (0x00) to 0.9 w (0x ff) in 3.62 mw steps for q3 and q4.
si3210/si3211 rev. 1.45 103 reset settings = 0000_0000 reset settings = 0000_0000 register 78. loop voltage sense bitd7d6d5d4d3d2d1d0 name lvsp lvs[5:0] type rr bit name function 7 reserved read returns zero. 6lvsp loop voltage sense polarity. this register reports the polarity of the differential loop voltage (v tip ? v ring ). 0 = positive loop voltage (v tip > v ring ). 1 = negative loop voltage (v tip < v ring ). 5:0 lvs[5:0] loop voltage sense magnitude. this register reports the magnitude of the differential loop voltage (v tip ?v ring ). the range is 0 v to 94.5 v in 1.5 v steps. register 79. loop current sense bitd7d6d5d4d3d2d1d0 name lcsp lcs[5:0] type rr bit name function 7 reserved read returns zero. 6lcsp loop current sense polarity. this register reports the polarity of the loop current. 0 = positive loop current (forward direction). 1 = negative loop current (reverse direction). 5:0 lcs[5:0] loop current sense magnitude. this register reports the magnitude of the loop current. the range is 0 ma to 78.75 ma in 1.25 ma steps.
si3210/si3211 104 rev. 1.45 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = 0000_0000 register 80. tip voltage sense bitd7d6d5d4d3d2d1d0 name vtip[7:0] type r bit name function 7:0 vtip[7:0] tip voltage sense. this register reports the real-time voltage at tip with respect to ground. the range is 0 v (0x00) to ?95.88 v (0xff) in .376 v steps. register 81. ring voltage sense bitd7d6d5d4d3d2d1d0 name vring[7:0] type r bit name function 7:0 vring[7:0] ring voltage sense. this register reports the real-time voltage at ring with respect to ground. the range is 0 v (0x00) to ?95.88 v (0xff) in .376 v steps. register 82. battery voltage sense 1 bitd7d6d5d4d3d2d1d0 name vbats1[7:0] type r bit name function 7:0 vbats1[7:0] battery voltage sense 1. this register is one of two registers that reports the real-time voltage at v bat with respect to ground. the range is 0 v (0x00) to ?95.88 v (0xff) in .376 v steps.
si3210/si3211 rev. 1.45 105 reset settings = 0000_0000 reset settings = xxxx_xxxx reset settings = xxxx_xxxx register 83. battery voltage sense 2 bitd7d6d5d4d3d2d1d0 name vbats2[7:0] type r bit name function 7:0 vbats2[7:0] battery voltage sense 2. this register is one of two registers that reports the real-time voltage at v bat with respect to ground. the range is 0 v (0x00) to ?95.88 v (0xff) in .376 v steps. register 84. transistor 1 current sense bitd7d6d5d4d3d2d1d0 name iq1[7:0] type r bit name function 7:0 iq1[7:0] transistor 1 current sense. this register reports the real-time current through q1. the range is 0 a (0x00) to 81.35 ma (0xff) in .319 ma steps. if etbe = 1, the reported value does not include the additional etbo/a current. register 85. transistor 2 current sense bitd7d6d5d4d3d2d1d0 name iq2[7:0] type r bit name function 7:0 iq2[7:0] transistor 2 current sense. this register reports the real-time current through q2. the range is 0 a (0x00) to 81.35 ma (0xff) in .319 ma steps. if etbe = 1, the reported value does not include the additional etbo/a current.
si3210/si3211 106 rev. 1.45 reset settings = xxxx_xxxx reset settings = xxxx_xxxx reset settings = xxxx_xxxx register 86. transistor 3 current sense bitd7d6d5d4d3d2d1d0 name iq3[7:0] type r bit name function 7:0 iq3[7:0] transistor 3 current sense. this register reports the real-time current through q3. the range is 0 a (0x00) to 9.59 ma (0xff) in 37.6 a steps. register 87. transistor 4 current sense bitd7d6d5d4d3d2d1d0 name iq4[7:0] type r bit name function 7:0 iq4[7:0] transistor 4 current sense. this register reports the real-time current through q4. the range is 0 a (0x00) to 9.59 ma (0xff) in 37.6 a steps. register 88. transistor 5 current sense bitd7d6d5d4d3d2d1d0 name iq5[7:0] type r bit name function 7:0 iq5[7:0] transistor 5 current sense. this register reports the real-time current through q5. the range is 0 a (0x00) to 80.58 ma (0xff) in .316 ma steps.
si3210/si3211 rev. 1.45 107 reset settings = xxxx_xxxx reset settings = 1111_1111 reset settings = xxxx_xxxx register 89. transistor 6 current sense bitd7d6d5d4d3d2d1d0 name iq6[7:0] type r bit name function 7:0 iq6[7:0] transistor 6 current sense. this register reports the real-time current through q6. the range is 0 a (0x00) to 80.58 ma (0xff) in .316 ma steps. register 92. dc-dc converter pwm period si3210 bitd7d6d5d4d3d2d1d0 name dcn[7] 1 dcn[5:0] type r/w r r/w si3211 bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 dcn[7:0] dc-dc converter period. this bit sets the pwm period for the dc-dc converter. the range is 3.906 s (0x40) to 15.564 s (0xff) in 61.035 ns steps. si3211 = reserved. bit 6 is fixed to one and read-only, so there are two ranges of operation: 3.906 s?7.751 s, used for mosfet transistor switching. 11.719 s?15.564 s, used for bjt transistor switching.
si3210/si3211 108 rev. 1.45 reset settings = 0001_0100 (si3210) reset settings = 0011_0100 (si3210m) reset settings = xxxx_xxxx register 93. dc-dc converter switching delay si3210 bitd7d6d5d4d3d2d1d0 name dccal dcpol dctof[4:0] type r/w r r/w si3211 bitd7d6d5d4d3d2d1d0 name type bit name function 7 dccal dc-dc converter peak current monitor calibration status (si3210 only). writing a one to this bit starts the dc-dc converter peak current monitor calibration rou- tine. 0 = normal operation. 1 = calibration being performed. si3211 = reserved. 6 reserved read returns zero. 5 dcpol dc-dc converter feed forward pin (dcff) polarity (si3210 only). this read-only register bit indicates the polarity relationship of the dcff pin to the dcdrv pin. two versions of the si3210 are offered to support the two relationships. 0 = dcff pin polarity is opposite of dcdrv pin (si3210). 1 = dcff pin polarity is same as dcdrv pin (si3210m). si3211 = reserved. 4:0 dctof[4:0] dc-dc converter minimum off time (si3210 only). this register sets the minimum off time for the pulse width modulated dc-dc converter control. t off =(dctof + 4) ? 61.035 ns. si3211 = reserved.
si3210/si3211 rev. 1.45 109 reset settings = 0000_0000 reset settings = 0000_0000 register 94. dc-dc converter pwm pulse width si3210 bitd7d6d5d4d3d2d1d0 name dcpw[7:0] type r si3211 bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 dcpw[7:0] dc-dc converter pulse width (si3210 only). pulse width of dcdrv is given by pw = (dcpw ? dctof ? 4) ? 61.035 ns. si3211 = reserved.
si3210/si3211 110 rev. 1.45 reset settings = 0001_1111 register 96. calibration control/status register 1 bitd7d6d5d4d3d2d1d0 name cal calsp calr calt cald calc calil type r/w r/w r/w r/w r/w r/w r/w bit name function 7 reserved read returns zero. 6cal calibration control/status bit. setting this bit begins calibration of the entire system. 0 = normal operation or calibration complete. 1 = calibration in progress. 5 calsp calibration speedup. setting this bit shortens the time allotted for v bat settling at the beginning of the calibration cycle. 0 = 300 ms 1=30ms 4calr ring gain mismatch calibration. for use with discrete solution only. when using the si3201, consult ?an35: si321x user?s quick reference guide? and follow instructions for manual calibration. 0 = normal operation or calibration complete. 1 = calibration enabled or in progress. 3calt tip gain mismatch calibration. for use with discrete solution only. when using the si3201, consult ?an35: si321x user?s quick reference guide? and follow instructions for manual calibration. 0 = normal operation or calibration complete. 1 = calibration enabled or in progress. 2cald differential dac gain calibration. 0 = normal operation or calibration complete. 1 = calibration enabled or in progress. 1calc common mode dac gain calibration. 0 = normal operation or calibration complete. 1 = calibration enabled or in progress. 0calil i lim calibration. 0 = normal operation or calibration complete. 1 = calibration enabled or in progress.
si3210/si3211 rev. 1.45 111 reset settings = 0001_1111 reset settings = 0001_0000 register 97. calibration control/status register 2 bitd7d6d5d4d3d2d1d0 name calm1 calm2 caldac caladc calcm type r/wr/wr/wr/wr/w bit name function 7:5 reserved read returns zero. 4calm1 monitor adc calibration 1. 0 = normal operation or calibration complete. 1 = calibration enabled or in progress. 3calm2 monitor adc calibration 2. 0 = normal operation or calibration complete. 1 = calibration enabled or in progress. 2caldac dac calibration. setting this bit begins calibration of the audio dac offset. 0 = normal operation or calibration complete. 1 = calibration enabled or in progress. 1 caladc adc calibration. setting this bit begins calibration of the audio adc offset. 0 = normal operation or calibration complete. 1 = calibration enabled or in progress. 0calcm common mode balance calibration. setting this bit begins calibration of the ac longitudinal balance. 0 = normal operation or calibration complete. 1 = calibration enabled or in progress. register 98. ring gain mismatch calibration result bitd7d6d5d4d3d2d1d0 name calgmr[4:0] type r/w bit name function 7:5 reserved read returns zero. 4:0 calgmr[4:0] gain mismatch of ie tracking loop for ring current.
si3210/si3211 112 rev. 1.45 reset settings = 0001_0000 reset settings = 0001_0001 reset settings = 0001_0001 register 99. tip gain mi smatch calibration result bitd7d6d5d4d3d2d1d0 name calgmt[4:0] type r/w bit name function 7:5 reserved read returns zero. 4:0 calgmt[4:0] gain mismatch of ie tracking loop for tip current. register 100. differential loop current gain calibration result bitd7d6d5d4d3d2d1d0 name calgd[4:0] type r/w bit name function 7:5 reserved read returns zero. 4:0 calgd[4:0] differential dac gain calibration result. register 101. common mode loop current gain calibration result bitd7d6d5d4d3d2d1d0 name calgc[4:0] type r/w bit name function 7:5 reserved read returns zero. 4:0 calgc[4:0] common mode dac gain calibration result.
si3210/si3211 rev. 1.45 113 reset settings = 0000_1000 reset settings = 1000_1000 reset settings = 0000_0000 register 102. current limit calibration result bitd7d6d5d4d3d2d1d0 name calgil[3:0] type r/w bit name function 7:5 reserved read returns zero. 3:0 calgil[3:0] current limit calibration result. register 103. monitor ad c offset calib ration result bitd7d6d5d4d3d2d1d0 name calmg1[3:0] calmg2[3:0] type r/w r/w bit name function 7:4 calmg1[3:0] monitor adc offset calibration result 1. 3:0 calmg2[3:0] monitor adc offset calibration result 2. register 104. analog dac/adc offset bitd7d6d5d4d3d2d1d0 name dacp dacn adcp adcn type r/wr/wr/wr/w bit name function 7:4 reserved read returns zero. 3dacp positive analog dac offset. 2dacn negative analog dac offset. 1 adcp positive analog adc offset. 0adcn negative analog adc offset.
si3210/si3211 114 rev. 1.45 reset settings = 0000_0000 reset settings = 0010_0000 reset settings = 0000_1000 register 105. dac of fset calibration result bitd7d6d5d4d3d2d1d0 name dacof[7:0] type r/w bit name function 7:0 dacof[7:0] dac offset cali bration result. register 106. common mode balance calibration result bitd7d6d5d4d3d2d1d0 name cmbal[5:0] type bit name function 7:6 reserved read returns zero. 5:0 cmbal[5:0] common mode balance calibration result. register 107. dc peak current monitor calibration result bitd7d6d5d4d3d2d1d0 name cmdcpk[3:0] type r/w bit name function 7:4 reserved read returns zero. 3:0 cmdcpk[3:0] dc peak current monito r calibration result.
si3210/si3211 rev. 1.45 115 reset settings = 0000_0000 reset settings = 0000_0000 register 108. enhancement enable note: the enhancement enable register and associated fe atures are available in sili con revisions c and later. si3210 bitd7d6d5d4d3d2d1d0 name ilimen fsken dcsu zsext lcve dcfil hysten type r/w r/w r/w r/w r/w r/w r/w si3211 bitd7d6d5d4d3d2d1d0 name ilimen fsken zsext swdb lcve hysten type r/w r/w r/w r/w r/w r/w bit name function 7ilimen current limit increase. when enabled, this bit temporarily increases th e maximum differential current limit at the end of a ring burst to enable a faster settling time to a dc linefeed state. 0 = the value programmed in ilim (direct register 71) is used. 1 = the maximum differential loop current limit is temporarily increased to 41 ma. 6 fsken fsk generation enhancement. when enabled, this bit will increase the clocki ng rate of tone gene rator 1 to 24 khz only when the rel bit (direct register 32, bit 6) is set. also, dedicated oscillator registers are used for fsk generation (indirect register s 99?104). audio tones are generated using this new higher frequency, and oscillator 1 acti ve and inactive timers have a finer bit res- olution of 41.67 s. this provides greater resolution during fsk caller id signal genera- tion. 0 = tone generator always clocked at 8 khz; osc1, osc1x., and osc1y are always used. 1 = tone generator module clocked at 24 khz and dedicated fsk registers used only when rel = 1; otherwise clocked at 8 khz. 5 dcsu dc-dc converter control speedup (si3210 only). when enabled, this bit invokes a multi-thresh old error control algorithm which allows the dc-dc converter to adjust more quickly to voltage changes. 0 = normal control algorithm used. 1 = multi-threshold error control algorithm used.
si3210/si3211 116 rev. 1.45 4 zsext impedance internal reference resistor disable. when enabled, this bit remove s the internal reference resistor used to synthesize ac impedances for 600 + 2.1 f and 900 + 2.16 f so that an external resistor reference may be used. 0 = internal resistor used to generate 600 + 2.1 f and 900 + 2.16 f impedances. 1 = internal resistor removed from circuit. 3swdb battery switch debounce (si3211 only). when enabled, this bit allows debouncing of t he battery switching circuit only when tran- sitioning from v bath to v batl external battery supplies (extbat = 1). 0 = no debounce used. 1 = 60 ms debounce period used. si3210 = reserved. 2lcve voltage-based loop closure. enables loop closure to be determined by the tip-to-ring voltage rather than loop cur- rent. 0 = loop closure determined by loop current. 1 = loop closure determined by tip-to-ring voltage. 1dcfil dc-dc converter squelch (si3210 only). when enabled, this bit squelches noise in the audio band from the dc-dc converter con- trol loop. 0 = voice band squelch disabled. 1 = voice band squelch enabled. 0 hysten loop closure hysteresis enable. when enabled, this bit allows hysteresis to the loop closure calculation. the upper and lower hysteresis thresholds are defined by indirect registers 28 and 43, respectively. 0 = loop closure hyst eresis disabled. 1 = loop closure hysteresis enabled. bit name function
si3210/si3211 rev. 1.45 117 4. indirect registers indirect registers are not directly mapped into memory but are accessible through the ida and iaa registers. a write to ida followed by a writ e to iaa is interpreted as a write request to an indirect register. in this case, the contents of ida are written to indirect memory at the location referenced by iaa at the next indirect register update. a write to iaa withou t first writing to ida is interpreted as a read request from an indirect register. in this case, the value located at iaa is written to ida at the next indirect register update. indirect registers are updated at a rate of 16 khz. for pending indirect register transfers, ias (direct register 31) will be one until serviced. in addi tion, an interrupt, ind (register 20), can be generated upon completion of the indirect transfer. 4.1. dtmf decoding all values are represented in 2s-complement format. note: the values of all indirect registers are undefined follow- ing the reset state. table 37. dtmf indirect registers summary addr.d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 0 row0[15:0] 1 row1[15:0] 2 row2[15:0] 3 row3[15:0] 4 col[15:0] 5 fwdtw[15:0] 6 revtw[15:0] 7 rowrel[15:0] 8 colrel[15:0] 9 row2[15:0] 10 col2[15:0] 11 pwrmin[15:0] 12 hotl[15:0]
si3210/si3211 118 rev. 1.45 table 38. dtmf indirect registers description addr. description reference page 0 dtmf row 0 peak magnitude pass ratio threshold. this register sets the minimum power ratio threshold for row 0 dtmf detection. if the ratio of power in row 0 to total power in the row band is greater than row0, a row 0 signal is detected. a value of 0x7ff0 corresponds to a 1.0 ratio. 47 1 dtmf row 1 peak magnitude pass ratio threshold. this register sets the minimum power ratio threshold for row 1 dtmf detection. if the ratio of power in row 1 to total power in the row band is greater than row1, a row 1 signal is detected. a value of 0x7ff0 corresponds to a 1.0 ratio. 47 2 dtmf row 2 peak magnitude pass ratio threshold. this register sets the minimum power ratio threshold for row 2 dtmf detection. if the ratio of power in row 2 to total power in the row band is greater than row2, a row 2 signal is detected. a value of 0x7ff0 corresponds to a 1.0 ratio. 47 3 dtmf row 3 peak magnitude pass ratio threshold. this register sets the minimum power ratio threshold for row 3 dtmf detection. if the ratio of power in row 3 to total power in the row band is greater than row3, a row 3 signal is detected. a value of 0x7ff0 corresponds to a 1.0 ratio. 47 4 dtmf column peak magnitude pass threshold. this register sets the minimum power ratio threshold for column dtmf detection; all columns use the same threshold. if the ratio of power in a particular column to total power in the column band is greater than col, a column detect for that particular column signal is detected. a value of 0x7ff0 corresponds to a 1.0 ratio. 47 5 dtmf forward twist threshold. this register sets the threshold for the power ratio of row power to column power. a value of 0x7f0 corresponds to a 1.0 ratio. 47 6 dtmf reverse twist threshold. this register sets the threshold for the power ratio of column power to row power. a value of 0x7f0 corresponds to a 1.0 ratio. 47 7 dtmf row ratio threshold. this register sets the threshold for the power ratio of highest power row to the other rows. a value of 0x7f0 corresponds to a 1.0 ratio. 47 8 dtmf column ratio threshold. this register sets the threshold for the power ratio of highest power column to the other col- umns. a value of 0x7f0 corresponds to a 1.0 ratio. 47 9 dtmf row second harmonic threshold. this register sets the threshold for the power ratio of peak row tone to its second harmonic. a value of 0x7f0 corresponds to a 1.0 ratio. 47 10 dtmf column second harmonic threshold. this register sets the threshold for the power ratio of peak column tone to its second harmonic. a value of 0x7f0 corresponds to a 1.0 ratio. 47 11 dtmf power minimum threshold. this register sets the threshold for the minimum total power in the dtmf calculation, under which the calculation is ignored. 47 12 dtmf hot limit threshold. this register sets the two-step agc in the dtmf path. 47
si3210/si3211 rev. 1.45 119 4.2. oscillators see functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. all values are represented in 2s- complement format. note: the values of all indirect registers are undefined follow- ing the reset state. shaded areas denote bits that can be read and written but sh ould be written to zeroes. table 39. oscillator indirect registers summary addr.d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 13 osc1[15:0] 14 osc1x[15:0] 15 osc1y[15:0] 16 osc2[15:0] 17 osc2x[15:0] 18 osc2y[15:0] 19 roff[5:0] 20 rco[15:0] 21 rngx[15:0] 22 rngy[15:0] 23 plsd[15:0] 24 plsx[15:0] 25 plsco[15:0]
si3210/si3211 120 rev. 1.45 table 40. oscillator indirect registers description addr. description reference page 13 oscillator 1 frequency coefficient. sets tone generator 1 frequency. 40 14 oscillator 1 amplitude register. sets tone generator 1 signal amplitude. 40 15 oscillator 1 initial phase register. sets initial phase of tone generator 1 signal. 40 16 oscillator 2 frequency coefficient. sets tone generator 2 frequency. 40 17 oscillator 2 amplitude register. sets tone generator 2 signal amplitude. 40 18 oscillator 2 initial phase register. sets initial phase of tone generator 2 signal. 40 19 ringing oscillator dc offset. sets dc offset component (v tip ?v ring ) to ringing waveform. the range is 0 to 94.5 v in 1.5 v increments. 42 20 ringing oscillator frequency coefficient. sets ringing generator frequency. 42 21 ringing oscillator amplitude register. sets ringing generator signal amplitude. 42 22 ringing oscillator initial phase register. sets initial phase of ringing generator signal. 42 23 pulse metering oscillator attack/decay ramp rate. sets pulse metering attack/decay ramp rate. 46 24 pulse metering oscillator amplitude register. sets pulse metering generator signal amplitude. 46 25 pulse metering oscillator frequency coefficient. sets pulse metering generator frequency. 46
si3210/si3211 rev. 1.45 121 4.3. digital programmable gain/attenua- tion see functional description sections of digital programmable gain/attenuation for guidelines on computing register values. all values are represented in 2s-complement format. note: the values of all indirect registers are undefined follow- ing the reset state. shaded areas denote bits that can be read and written but sh ould be written to zeroes. table 41. digital programmable gain/attenuation indirect registers summary addr.d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 26 dacg[11:0] 27 adcg[11:0] table 42. digital programmable gain/attenuation indirect registers description addr. description reference page 26 receive path digital to analog converter gain/attenuation. this register sets gain/attenuation for the receiv e path. the digitized signal is effectively mul- tiplied by dacg to achieve gain/attenuat ion. a value of 0x00 corresponds to ? ? db gain (mute). a value of 0x400 corres ponds to unity gain. a value of 0x7ff corresponds to a gain of 6 db. 48 27 transmit path analog to digi tal converter ga in/attenuation. this register sets gain/attenuat ion for the transmit path. the di gitized signal is effectively multiplied by adcg to achi eve gain/attenuation. a val ue of 0x00 corresponds to ? ? db gain (mute). a value of 0x400 corres ponds to unity gain. a value of 0x7ff corresponds to a gain of 6 db. 48
si3210/si3211 122 rev. 1.45 4.4. slic control see descriptions of linefeed interface and power monitoring for guidelines on computing register values. all values are represented in 2s-complement format. note: the values of all indirect registers are undefined follow- ing the reset state. shaded areas denote bits that can be read and written but sh ould be written to zeroes. table 43. slic control indirect registers summary addr.d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 28 lcrt[5:0] 29 rptp[5:0] 30 cml[5:0] 31 cmh[5:0] 32 ppt12[7:0] 33 ppt34[7:0] 34 ppt56[7:0] 35 nclr[12:0] 36 nrtp[12:0] 37 nq12[12:0] 38 nq34[12:0] 39 nq56[12:0] 40 vcmr[3:0] 41 vmind[3:0]* 42 43 lcrtl[5:0] *note: si3210 only.
si3210/si3211 rev. 1.45 123 table 44. slic control indirect registers description addr. description reference page 28 loop closure threshold. loop closure detection threshold. this regist er defines the upper bounds threshold if hys- teresis is enabled (direct register 108, bit 0 ). the range is 0?80 ma in 1.27 ma steps. 35 29 ring trip threshold. ring trip detection threshold during ringing. 45 30 common mode minimum threshold for speed-up. this register defines the negative common mode voltage threshold. exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. the range is 0?23.625 v in 0.375 v steps. 31 common mode maximum threshold for speed-up. this register defines the positive common mode voltage threshold. exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. the range is 0?23.625 v in 0.375 v steps. 32 power alarm threshold for transistors q1 and q2. 33 33 power alarm threshold for transistors q3 and q4. 33 34 power alarm threshold for transistors q5 and q6. 33 35 loop closure filter coefficient. 35 36 ring trip filter coefficient. 45 37 thermal low pass filter pole for transistors q1 and q2. 33 38 thermal low pass filter pole for transistors q3 and q4. 33 39 thermal low pass filter pole for transistors q5 and q6. 33 40 common mode bias adjust during ringing. recommended value of 0 decimal. 42 41 dc-dc converter v ov voltage (si3210 only). this register sets the overhead voltage, v ov , to be supplied by the dc-dc converter. when the vov bit = 0 (direct register 66, bit 4), v ov should be set between 0 and 9 v (vmind = 0 to 6h). when the vov bit = 1, v ov should be set between 0 and 13.5 v (vmind = 0 to 9h). 36 42 reserved. 43 loop closure threshold?lower bound. this register defines the lower threshold for loop closure hysteresis, which is enabled in bit 0 of direct register 108. the range is 0?80 ma in 1.27 ma steps. 35
si3210/si3211 124 rev. 1.45 4.5. fsk control for detailed instructions on fsk signal generation, refer to ?application note 32: fsk generation? (an32). these registers support enhanced fsk generation mode, which is enabled by setting fsken = 1 (direct register 108, bit 6) and rel = 1 (direct register 32, bit 6). table 45. fsk control indirect registers summary addr.d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 99 fsk0x[15:0] 100 fsk0[15:0] 101 fsk1x[15:0] 102 fsk1[15:0] 103 fsk01[15:0] 104 fsk10[15:0] table 46. fsk control indirect registers description addr. description reference page 99 fsk amplitude coefficient for space. when fsken = 1 and rel = 1, this register se ts the amplitude to be used when gener- ating a space or ?0?. when the active timer (oat1) expires, the value of this register is loaded into oscillato r 1 instead of osc1x. 42 and an32 100 fsk frequency coefficient for space. when fsken = 1 and rel = 1, this register se ts the frequency to be used when gener- ating a space or ?0?. when the active timer (oat1) expires, the value of this register is loaded into oscillato r 1 instead of osc1. 42 and an32 101 fsk amplitude coefficient for mark. when fsken = 1 and rel = 1, this register se ts the amplitude to be used when gener- ating a mark or ?1?. when the active timer (oat 1) expires, the value of this register is loaded into oscillato r 1 instead of osc1x. 42 and an32 102 fsk frequency coefficient for mark. when fsken = 1 and rel = 1, this register se ts the frequency to be used when gener- ating a mark or ?1?. when the active timer (oat 1) expires, the value of this register is loaded into oscillato r 1 instead of osc1. 42 and an32 103 fsk transition parameter from 0 to 1. when fsken = 1 and rel = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a space (0) to a mark (1). 42 and an32 104 fsk transition parameter from 1 to 0. when fsken = 1 and rel = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a mark (1) to a space (0). 42 and an32
si3210/si3211 rev. 1.45 125 5. pin descriptions: si3210/11 qfn pin # tssop pin # name description 35 1 cs chip select. active low. when inactive, sclk and sdi are ignored and sdo is high impedance. when active, the serial port is operational. 36 2 int interrupt. maskable interrupt output. open drain output for wire-ored operation. 37 3 pclk pcm bus clock. clock input for pcm bus timing. 38 4 drx receive pcm data. input data from pcm bus. 15 dtx transmit pcm data. output data to pcm bus. 2 6 fsync frame synch. 8 khz frame synchronization signal for the pcm bus. may be short or long pulse format. 3 7 reset reset. active low input. hardware reset used to place all control registers in the default state. 4 8 sdch/dio1 dc monitor/general purpose i/o. dc-dc converter monitor input used to detect overcurrent situations in the converter (si3210 only). general purpose i/o (si3211 only). tssop 27 28 29 30 31 34 33 32 cs int pclk dtx fsync reset sdch/dio1 sclk sdi sdithru sdo dcff/dout dcdrv/dcsw gndd test drx 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 14 sdcl/dio2 v dda1 iref capp itipn vddd v dda2 itipp 35 36 37 38 qgnd capm iringp iringn stipdc sringdc stipe svbat sringe igmp gnda igmn sringac stipac 15 16 17 18 19 24 23 22 21 20 27 28 29 30 31 34 33 32 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 14 35 36 37 38 15 16 17 18 19 24 23 22 21 20 qfn dtx fsync reset sdch/dio1 sdcl/dio2 v dda1 iref capp qgnd capm stipdc sringdc stipe svbat sringe stipac sringac igmn gnda igmp iringn iringp v dda2 itipp itipn vddd gndd test dcff/dout dcdrv/dcsw sdithru sdo sdi sclk cs int pclk drx
si3210/si3211 126 rev. 1.45 5 9 sdcl/dio2 dc monitor/general purpose i/o. dc-dc converter monitor input used to detect overcurrent situations in the converter (si3210 only). general purpose i/o (si3211 only). 6 10 vdda1 analog supply voltage. analog power supply for internal analog circuitry. 711 iref current reference. connects to an external resistor used to provide a high accuracy reference current. 8 12 capp slic stabilization capacitor. capacitor used in low pass filter to stabilize slic feedback loops. 9 13 qgnd component reference ground. 10 14 capm slic stabilization capacitor. capacitor used in low pass filter to stabilize slic feedback loops. 11 15 stipdc tip sense. analog current input used to sense voltage on the tip lead. 12 16 sringdc ring sense. analog current input used to sense voltage on the ring lead. 13 17 stipe tip emitter sense. analog current input used to sense voltage on the q6 emitter lead. 14 18 svbat v bat sense. analog current input used to sense voltage on dc-dc converter output voltage lead. 15 19 sringe ring emitter sense. analog current input used to sense voltage on the q5 emitter lead. 16 20 stipac tip transmit input. analog ac input used to detect voltage on the tip lead. 17 21 sringac ring transmit input. analog ac input used to detect voltage on the ring lead. 18 22 igmn transconductance amplifier external resistor. negative connection for transconductance gain setting resistor. 19 23 gnda analog ground. ground connection for internal analog circuitry. 20 24 igmp transconductance amplifier external resistor. positive connection for transco nductance gain setting resistor. 21 25 iringn negative ring current control. analog current output driving q3. 22 26 iringp positive ring current control. analog current output driving q2. qfn pin # tssop pin # name description
si3210/si3211 rev. 1.45 127 23 27 vdda2 analog supply voltage. analog power supply for internal analog circuitry. 24 28 itipp positive tip current control. analog current output driving q1. 25 29 itipn negative tip current control. analog current output driving q4. 26 30 vddd digital supply voltage. digital power supply for internal digital circuitry. 27 31 gndd digital ground. ground connection for internal digital circuitry. 28 32 test test. enables test modes for silicon labs inte rnal testing. this pin should always be tied to ground for normal operation. 29 33 dcff/dout dc feed-forward/high current general purpose output. feed-forward drive of external bipolar transistors to improve dc-dc converter efficiency (si3210 only). high current output pin (si3211 only). 30 34 dcdrv/dcsw dc drive/battery switch. dc-dc converter control signal output whic h drives external bipolar transistor (si3210 only). battery switch control signal output which drives external bipolar transistor (si3211 only). 31 35 sdithru sdi passthrough. cascaded sdi output signal for daisy-chain mode. 32 36 sdo serial port data out. serial port control data output. 33 37 sdi serial port data in. serial port control data input. 34 38 sclk serial port bit clock input. serial port clock input. controls the se rial data on sdo and latches the data on sdi. qfn pin # tssop pin # name description
si3210/si3211 128 rev. 1.45 6. pin descriptions: si3201 pin # name input/ output description 1 tip i/o tip output ?connect to the tip lead of the subscriber loop. 2, 6, 9, 12 nc ? no internal connection ?do not connect to any electrical signal. 3 ring i/o ring output ?connect to the ring lead of the subscriber loop. 4vbat? operating battery voltage ?connect to the battery supply. 5vbath? high battery voltage ?this pin is internally connected to vbat. 7gnd? ground ?connect to a low impedance ground plane. 8vdd? supply voltage ?main power supply for all internal circuitry. connect to a 3.3 v or 5 v supply. decouple locally with a 0.1 ? f/6 v capacitor. 10 sringe o ring emitter sense output ?connect to the sringe pin of the si321x pin. 11 stipe o tip emitter sense output ?connect to the stipe pin of the si321x pin. 13 iringn i negative ring current control ?connect to the iringn lead of the si321x. 14 iringp i positive ring current drive ?connect to the iringp lead of the si321x. 15 itipn i negative tip current control ?connect to the itipn lead of the si321x. 16 itipp i positive tip current control ?connect to the itipp lead of the si321x. bottom-side exposed pad ? exposed thermal pad ?connect to the bulk ground plane. 116 215 314 413 512 611 710 89 itipp iringp iringn nc stipe sringe nc itipn tip nc ring vbath gnd nc vdd vbat
si3210/si3211 rev. 1.45 129 7. ordering guide chip description dc-dc converter dtmf decoder dcff pin output package lead-free and rohs- compliant temperature si3210-e-fm proslic ?? dcdrv qfn-38 yes 0 to 70 c si3210-e-gm proslic ?? dcdrv qfn-38 yes ?40 to 85 c si3210m-e-fm proslic ?? dcdrv qfn-38 yes 0 to 70 c si3210m-e-gm proslic ?? dcdrv qfn-38 yes ?40 to 85 c si3210-kt proslic ?? dcdrv tssop-38 no 0 to 70 c si3210-bt proslic ?? dcdrv tssop-38 no ?40 to 85 c si3210-ft proslic ?? dcdrv tssop-38 yes 0 to 70 c si3210-gt proslic ?? dcdrv tssop-38 yes ?40 to 85 c si3210m-kt proslic ?? dcdrv tssop-38 no 0 to 70 c si3210m-bt proslic ?? dcdrv tssop-38 no ?40 to 85 c si3210m-ft proslic ?? dcdrv tssop-38 yes 0 to 70 c si3210m-gt proslic ?? dcdrv tssop-38 yes ?40 to 85 c si3211-kt proslic ? n/a tssop-38 no 0 to 70 c si3211-bt proslic ? n/a tssop-38 no ?40 to 85 c si3211-e-ft proslic ? n/a tssop-38 yes 0 to 70 c si3211-e-gt proslic ? n/a tssop-38 yes ?40 to 85 c si3211-e-fm proslic ? n/a qfn-38 yes 0 to 70 c si3211-e-gm proslic ? n/a qfn-38 yes ?40 to 85 c si3201-ks linefeed interface n/a soic-16 no 0 to 70 c si3201-bs linefeed interface n/a soic-16 no ?40 to 85 c si3201-fs linefeed interface n/a soic-16 yes 0 to 70 c si3201-gs linefeed interface n/a soic-16 yes ?40 to 85 c note: add an ?r? at the end of the device to denote tape and reel; 2500 quantity per reel.
si3210/si3211 130 rev. 1.45 table 47. evaluation kit ordering guide item supported proslic description linefeed interface si3210ppqx-evb si3210-qfn eval board, daughter card discrete si3210ppq1-evb si3210-q fn eval board, daughter card si3201 si3210pptx-evb si3210-tssop eval board, daughter card discrete si3210ppt1-evb si3210-tssop eval board, daughter card si3201 si3210mpptx-evb si3210m-tssop eval board, daughter card discrete si3210mppt1-evb si3210m-tssop eval board, daughter card si3201 si3211pptx-evb si3211-tssop eval board, daughter card discrete
si3210/si3211 rev. 1.45 131 8. package outline: 38-pin qfn figure 33 illustrates the package details for the si321x. table 48 lists the val ues for the dimensions shown in the illustration. figure 33. 38-pin quad flat no-lead package (qfn) table 48. package diagram dimensions 1,2,3 symbol millimeters min nom max a 0.75 0.85 0.95 a1 0.00 0.01 0.05 b 0.18 0.23 0.30 d5.00 bsc. d2 3.10 3.20 3.30 e0.50 bsc. e7.00 bsc. e2 5.10 5.20 5.30 l 0.35 0.45 0.55 l1 0.03 0.05 0.08 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1982. 3. recommended card reflow profile is per the jedec/ipc j-std-020c specification fo r small body components. bottom side exposed pad 3.2 x 5.2 mm
si3210/si3211 132 rev. 1.45 9. package outline: 38-pin tssop figure 34 illustrates the package details for the si321x. table 49 lists the val ues for the dimensions shown in the illustration. figure 34. 38-pin thin shrink small outline package (tssop) table 49. package diagram dimensions symbol millimeters min nom max a? ?1.20 a1 0.05 ? 0.15 a2 0.80 1.00 1.05 b 0.17 ? 0.27 c 0.09 ? 0.20 d 9.60 9.70 9.80 e6.40 bsc e1 4.30 4.40 4.50 e0.50 bsc l 0.45 0.60 0.75 l2 0.25 bsc ? 0 ? 8 aaa 0.10 bbb 0.08 ccc 0.20
si3210/si3211 rev. 1.45 133 10. package out line: 16-pin esoic figure 35 illustrates the package details for the si3201. table 50 lists the valu es for the dimensions shown in the illustration. figure 35. 16-pin thermal enhanced small outline integrated circuit (esoic) package
si3210/si3211 134 rev. 1.45 table 50. package diagram dimensions symbol millimeters min max a?1.75 a1 0.00 0.15 a2 1.25 ? b0.310.51 c0.170.25 d 9.90 bsc d1 3.45 3.65 e 6.00 bsc e1 3.90 bsc e2 2.20 2.40 e 1.27 bsc l0.401.27 l2 0.25 bsc h0.250.50 ? 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25
si3210/si3211 rev. 1.45 135 d ocument c hange l ist revision 1.41 to revision 1.42 ? 16-pin esoic dimension a1 corrected in table 49 on page 132. ? delay time between chip selects, t cs , changed from 220 ns to 440 ns in table 10 on page 15. ? c10 changed from 22 nf to 0.1 f in figure 10 on page 19. ? c18, c19 changed from 1.0 f to 4.7 f in figure 12 on page 22. ? recommended value for indirect register 40 changed from 6 to 0 in table 44 on page 123. ? added qfn package option. revision 1.42 to revision 1.43 ? table 16, ?si3210/si3210m external component values?discrete solution,? on page 25. ?? added to-92 transistor suppliers to bom. ? "7. ordering guide" on page 129 ?? updated to include product revision designator. ?? ?lead-free? changed to ?lead-free and rohs- compliant? ? figure 9, ?si3210/si3210m application circuit using si3201,? on page 17. ?? added additional decoupling components to vdda1, vdda2, and vddd. ? figure 12, ?si3211 typical application circuit using si3201,? on page 22. ?? added additional decoupling components to vdda1, vdda2, and vddd. ? figure 13, ?si3210/si3210m typical application circuit using discrete components,? on page 24. ?? added additional decoupling components to vdda1, vdda2, and vddd. ?? added optional components to stipe, sringe, and svbat pins to improve idle channel noise. ? figure 14, ?si3211 typical application circuit using discrete solution,? on page 26. ?? added additional decoupling components to vdda1, vdda2, and vddd. ?? added optional components to stipe, sringe, and svbat pins to improve idle channel noise. ? table 50, ?package diagram dimensions,? on page 134 ?? changed a1 max dimension from 0.10 to 0.15. revision 1.43 to revision 1.44 ? updated figure 9. ?? moved the schematic for the supply filtering network for v dda1 , v dda2 , and v ddd from the bottom of the diagram to the top. ?? moved the symbol for c26 closer to the v bath pin on the si3201 symbol. ?? changed r26 to 10 k ? . ?? added note 5. ? updated figure 12. ?? moved the schematic for the supply filtering network for v dda1 , v dda2 , and v ddd from the bottom of the diagram to the top. ?? moved the symbol for c9 closer to the v bath pin on the si3201 symbol. ?? changed r26 to 10 k ? . ?? added note 4. ? updated figure 13. ?? moved the schematic for the supply filtering network for v dda1 , v dda2 , and v ddd from the bottom of the diagram to the top. ?? added note 5 and moved the symbol for c26 to better illustrate its optimal position in a board layout. ?? changed r26 to 10 k ? . ?? added note 6. ? updated figure 14. ?? moved the schematic for the supply filtering network for v dda1 , v dda2 , and v ddd from the bottom of the diagram to the top. ?? added note 3 and moved the symbol for c26 to better illustrate its optimal position in a board layout. ?? added note 4. ?? changed r26 to 10 k ? . ?? corrected connection between d1 and the linefeed components. ?? added note 5 ? updated table 3. ?? corrected longitudinal current per pin for ebto/ ebta = 10 to 12 ma. ? updated table 8. ?? filled-in typical values for i vdd and i bat for v ddd , v dda =3.3v. ? updated table 11. ?? renamed "pclk period jitter tolerance" to "pclk-to-fsync jitter tolerance". ?? added note 2. ? updated table 12. ?? changed current rating of l2 to 150 ma. ?? added new row for r26 and changed the value to 10 k ? . ?? added title for an45 to description of r28 and r29. ?? added column for component package type. ?? added note 1. ? updated table 13. ?? added column for component package type. ? updated table 14. ?? added column for component package type. ? updated table 15. ?? changed current rating of l2 to 150 ma. ?? added new row for r26 and changed the value to 10 k ? . ?? rearranged the rows for r8 through r32 to be in numerical order. ?? added column for component package type.
si3210/si3211 136 rev. 1.45 ?? added note 1. ? updated table 16. ?? changed current rating of l2 to 150 ma. ?? corrected missing reference to r5. ?? added new row for r26 and changed the value to 10 k ? . ?? added title for an45 to description of r28 and r29. ?? added column for component package type. ?? added note 1. ? updated table 17. ?? added new row for r26 and changed the value to 10 k ? . ?? added column for component package type. ?? added note 1. ? updated table 18. ?? added column for component package type. ? updated table 19. ?? added column for component package type. ? updated table 36. ?? added mnemonic for bit 7 of direct register 1 (pni2). ?? changed name of register 94 to match the name in the description of register 94. ? updated table 47. ?? removed unsupported evaluation kit part numbers. ? updated register 1. ?? added mnemonic and description of bit 7 (pni2). ? updated register 75. ?? clarified the description of v batl for si3211. ? updated "2.1.6. loop closure transition detection" on page 35. ?? modified first and second paragraphs to indicate that a loop closure event signals a transition from on-hook to off-hook or from off-hook to on-hook. ? updated "2.4.2. sinusoidal ringing" on page 43. ?? modified second paragraph to indicate the minimum allowed peak tip-to-ring ringing voltage depends on the linefeed state; i.e. forward-active or reverse-active. ? updated "2.9. clock generation" on page 51. ?? modified first paragraph to indicate that 768 khz and 1.536 mhz are not valid rates for gci mode. ? updated "2.12. pcm interface" on page 55. ?? modified first paragraph to indicate that 768 khz and 1.536 mhz are not valid rates for gci mode. ? updated "9. package outlin e: 38-pin tssop" on page 132 with more detailed package drawing. ? updated "10. package outline: 16-pin esoic" on page 133 with more detailed package drawing. revision 1.44 to revision 1.45 ? added si3211-e-ft and si3211-e-gt to ordering guide ? clarified ordering guide ?? replaced "x" with revision letter "e" in all ordering codes requiring a revision letter ?? removed note 1 from ordering guide ? added qfn-38 image to front page.
si3210/si3211 rev. 1.45 137 n otes :
si3210/si3211 138 rev. 1.45 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email:proslicinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and prosli c are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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